Arito Ogawa

Symmetrical threshold voltage in complementary metal-oxide-semiconductor field-effect transistors with HfAlOx(N) achieved by adjusting Hf∕Al compositional ratio

We propose a method for restoring the symmetry in the threshold voltage (Vth) in complementary metal-oxide-semiconductor field-effect transistors (FETs) with a Hf-based high-k dielectric. This technique is based on the Al composition adjustment in the HfAlOx(N) dielectric film to achieve the symmetric Vth. The asymmetry of ∣Vth∣ in n and p metal-oxide-semiconductor FET (MOSFETs) due to the Fermi-level pinning at the interface between the poly-Si gate electrode and Hf-based high-k dielectric is considered to be induced independently by two kinds of interfacial dipoles. The adjustment of the Al content in HfAlOx(N) enables us to balance these dipoles. Vth values of n- and p-MOSFETs are shifted in the positive direction as the Al content in HfAlOx(N) increases. Symmetrical Vth values can be obtained for poly-Si and single fully silicided nickel gate electrodes when the Al contents are about 25 and 7at.% in HfAlOx(N), respectively.

Mechanism of Gradual Increase of Gate Current in High-K Gate Dielectrics and Its Application to Reliability Assessment

To establish the reliability model of the high-k gate dielectrics in the EOT-scaled regime, the gradual increase of the leakage current during the stress time, which makes the precise detection of the breakdown harder, has been studied. It has been clarified that multiple occurrence of soft breakdown (SBD) at plural local spots is the cause of the gradual increase, along with a large initial leakage current. Based on this mechanism, a model for the gradual increase has been proposed. The proposed multiple SBD-based model gives us a warning that we will obtain inaccurate values of the Weibull slope (beta) and the time to breakdown (TBD or eta), if we do not take into account this mechanism. To avoid such evaluations, a simple reliability assessment method has been also proposed, which realizes the accurate prediction of the breakdown statistics even without experimental detections of the first breakdown

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

Quantitative analysis of contribution of initial traps to breakdown in HfAlO/sub x//SiO/sub 2/ stacked gate dielectrics

We have demonstrated that the TDDB reliability should be predicted with the trap generation rate extracted excluding the amount of initial traps and that the initial trap cannot explain the low Weibull slope /spl beta/ observed in high-k stacks.

Scalability of TiN/HfAlO/TiN MIM DRAM capacitor to 0.7-nm-EOT and beyond

We have proposed guiding principle of material selection of electrode/dielectric combination for MIM DRAM capacitors by theoretically taking the tunneling barrier height into account. Accordingly, we found that phase-controlled HfO2 (HfAlO) with TiN electrode is promising. TiN/HfAlO/TiN MIM capacitors with an ultra-thin Al2O3 on the bottom TiN electrode were fabricated and an EOT of 0.7 nm with a leakage current of 80 nA/cm2 was successfully achieved.

Roles of high-k and interfacial layers on TDDB reliability studied with HfAlO X /SiO 2 stacked gate dielectrics

The objective of this paper is to clarify the primary roles of high-k layer and of interfacial layer on the TDDB lifetime in order to provide a guideline for realizing adequate TDDB reliability and also for the further high-k material selection. HfAlO(N)/SiO(N) and HfON/SiON stacked gate dielectrics has been fabricated with various deposition conditions and thicknesses. Electrical characteristics were evaluated with n+ and p+ poly-Si gated n- and p-channel MOSFETs. It was found that TDDB reliability depends of the thickness of high-k layer, regardless of the nitrogen concentration.

Theoretical Screening of Candidate Materials for DRAM Capacitors and Experimental Demonstration of a Cubic-Hafnia MIM Capacitor

To screen candidate materials for dynamic random-access memory capacitors, the tunneling probability at a constant equivalent oxide thickness (EOT) of metal-insulator-metal (MIM) capacitors was theoretically maximized according to a tradeoff between permittivity and band offset. As a result, it was found that cubic HfO2 with a TiN electrode is a promising candidate. TiN/Al-doped HfO2/TiN MIM capacitors were fabricated by inserting Al2O3 layers for phase control of HfO2 and for suppression of TiN oxidation. The fabricated capacitors exhibit leakage current of 80 nA/cm2 at 1 V and EOT of 0.7 nm. Moreover, the main leakage current was estimated to originate from oxygen vacancies.

Low-Threshold-Voltage HfOxN p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Partially Silicided Platinum Gate Electrode

HfOxN p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with a low threshold voltage (|Vth|) were successfully fabricated using a partially silicided (PASI) platinum gate electrode for scaled complementary MOS (CMOS). The PASI platinum (PASI-PtSi) gate electrode is composed of a monoclinic-Pt3Si phase in the vicinity of a HfOxN dielectric. The reduced silicon content of the PASI gate electrodes is effective in suppressing the Fermi-level pinning on the Hf-based gate dielectrics which induces a significant |Vth| shift in p-channel MOSFETs. It is shown that the |Vth| of HfOxN p-channel MOSFETs with the PASI-PtSi gate electrode is sufficiently low and applicable to low-standby-power devices. The mobility of the holes at 0.8 MV/cm is as high as about 90% of the universal mobility. It is concluded that the PASI technology in which the gate electrode has a reduced silicon content is useful for scaled CMOSs.

Impact of air-induced poly-Si/oxynitride interface layer degradation on gate-edge leakage

The air-sensitivity of the poly-Si interface in MOS transistors and its impact on the electrical properties are studied. It is found that the gate leakage localized near the side of air-exposed edges is possibly caused by air-induced degradation of the poly-Si interface, which supplies mobile NH3-like species to the gate edge side surface, resulting in the formation of a non-stoichiometric as well as impurity-retaining, hence conductive, SiOxNy edge layer. Control of the air-sensitive interfacial oxynitride and its NH3-related decomposition reaction is considered to be essential for improving the gate-edge leakage.

Si-Capped Annealing of HfO2-based Dielectrics for Suppressing Interface Layer Growth and Oxygen Out-Diffusion

Masashi Takahashi, Hideki Satake, Masaru Kadoshima, Arito Ogawa, Kunihiko Iwamoto, Hiroyuki Ota, Toshihide Nabatame and Akira Toriumi 3 MIRAI-ASET, AIST Tsukuba West 7, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan Phone: +81-29-849-1553 Fax: +81-29-849-1529 E-mail: takahashi.masashi@mirai.aist.go.jp MIRAI-ASRC, AIST Tsukuba West 7, 16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656, Japan