Nobuyuki Mise

Symmetrical threshold voltage in complementary metal-oxide-semiconductor field-effect transistors with HfAlOx(N) achieved by adjusting Hf∕Al compositional ratio

We propose a method for restoring the symmetry in the threshold voltage (Vth) in complementary metal-oxide-semiconductor field-effect transistors (FETs) with a Hf-based high-k dielectric. This technique is based on the Al composition adjustment in the HfAlOx(N) dielectric film to achieve the symmetric Vth. The asymmetry of ∣Vth∣ in n and p metal-oxide-semiconductor FET (MOSFETs) due to the Fermi-level pinning at the interface between the poly-Si gate electrode and Hf-based high-k dielectric is considered to be induced independently by two kinds of interfacial dipoles. The adjustment of the Al content in HfAlOx(N) enables us to balance these dipoles. Vth values of n- and p-MOSFETs are shifted in the positive direction as the Al content in HfAlOx(N) increases. Symmetrical Vth values can be obtained for poly-Si and single fully silicided nickel gate electrodes when the Al contents are about 25 and 7at.% in HfAlOx(N), respectively.

Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects

We have clarified the impact on reliability of La incorporation into the HfSiON gate dielectrics nMOSFETs (PBTI, TDDB). Although La incorporation is effective for pre-existing defect suppression, stress induced defect generation is more sensitive to stress voltage and temperature. This is caused by the elevation of the energy level of oxygen vacancy and high ionicity of La-O bond. The origin of defects is thought to be oxygen vacancy related defects, generated under positive stress and they are common to PBTI and TDDB degradation.

(111)-Faceted Metal Source and Drain for Aggressively Scaled Metal/High-

We have proposed a (111)-faceted metal source and drain (S/D) with a metal gate and a high-k gate dielectric for aggressively scaled complementary metal-insulator-semiconductor field-effect transistors (MISFETs). The metal S/D is formed by epitaxially grown nickel disilicide. N-type or p-type dopants are segregated in the atomically flat metal/Si interfaces that help to reduce the effective Schottky barrier height between the epitaxial metal and silicon. Therefore, a single type of metal S/D can work for both n-type and p-type MISFETs. The dopant segregation is realized by an ion implantation into the epitaxial silicides and a subsequent low-temperature annealing. Operations of 6-nm-long n-type and p-type silicon-on-insulator MISFETs that came with a fully silicided gate electrode and a high-k gate dielectric were experimentally demonstrated. The excellent short-channel effect immunity due to the trapezoidal channel was also verified by numerical simulation.

k

We investigate an origin of the Fermi-level pinning at the gate electrode/HfO/sub x/(N) interface, and propose a new technology for tuning the work function with a partial silicidation of Pt on HfO/sub x/ (N). It is clearly shown that the effective work functions (/spl Phi/ /sub m,eff/) of fully silicided (FUSI) NiSi and PtSi on HfO/sub x/(N) are rigidly fixed due to the Fermi-level pinning, and that the impurity doping does not help changing /spl Phi/ /sub m,eff/ at all. The large flatband voltage (VFB) shifts of FUSI PtSi MOSFETs have been observed irrespective of Si deposition processes. On the basis of these new findings, nMOSFET with pinned n+poly-Si and pMOSFET with partially pinned PtSi on HfO/sub x/ (N) for a balanced CMOS have been proposed, and both of them have shown good electrical properties. Furthermore, it is experimentally discussed that the control of the Si atom content at the PtSi/sub x//HfO/sub 2/ interface is a key factor to relax the pinning effect. The partial silicidation technology will be a most feasible method for advanced metal gate CMOS.

MISFETs

We have proposed a single metal/dual high-k (SMDH), low-Vth gate stack for aggressively scaled CMISFETs. The Vth is controlled by MgO- and Al2O3-containing high-k for n and pMISFETs, respectively. The gate profile can be more easily controlled by taking advantage of a common W/TiN gate stack on both high-ks. We have successfully obtained 0.21 and -0.33 V of Vth for a 1-mum long n and pMISFET by the proposed SMDH gate stacks. We also found that MgO suppresses PBTI and that it enhances electron mobility.

Partial silicides technology for tunable work function electrodes on high-k gate dielectrics - Fermi level pinning controlled PtSi/sub x/ for HfO/sub x/ (N) pMOSFET

The behavior of traps in physical-vapor-depostited-TiN/SiO2/Si, which had been created in annealing process, was investigated by positron annihilation spectroscopy and X-ray photoelectron spectroscopy. The traps were found to be located at both the TiN/SiO2 and SiO2/Si interfaces, and in the SiO2-bulk. The high-temperature annealing decreased the concentration of the traps in bulk SiO2 and at SiO2/Si interface. Backside X-ray photoelectron spectroscopy (XPS) analysis of TiN/SiO2 suggested the formation of titanium oxynitride (TiON) at the TiN/SiO2 interface, and the amount of TiON formation was reduced by high-temperature annealing. The number of traps at the TiN/SiO2 interface increased with high-temperature annealing, in the case of the increased TiN deposition temperature of 300 °C.

Single Metal/Dual High-k Gate Stack with Low V th and Precise Gate Profile Control for Highly Manufacturable Aggressively Scaled CMISFETs

The effect of gate metal film stress on the performance of gate-last metal–oxide–semiconductor field-effect transistors (MOSFETs) with a W/TiN/SiO2 gate stack was investigated. The channel strain induced by the electrode film was controlled by the W film stress. The W film stress was determined by the deposition method and film thickness. The compressive and tensile stresses of the electrode film enhance nFET and pFET performances, respectively. The enhancements of the performances are introduced not only by the stress of the film on the channel but also by the stress of the film on the side in the groove of the gate-last MOSEFTs. Metal electrode stress can be a further controlling factor in the performance of scaled devices.

Impact of High Temperature Annealing on Traps in Physical-Vapor-Deposited-TiN/SiO2/Si Analyzed by Positron Annihilation

This paper reports novel, non-epitaxial raised source/drain (S/D) approaches to decrease the parasitic external resistance in complementary metal–oxide–semiconductor field-effect transistors (CMOSFETs) fabricated on ultrathin silicon on insulator (UTSOI). This technique utilizes a metal Schottky S/D process with dopant segregation. Selectively formed NiSi2 with dopant segregation fabricated by laser-spike annealing (LSA) significantly lowered effective Shottky-barrier height and, thereby, lowered contact resistance (ρc). Satisfying the requirements of UTSOI MOSFETs in the 32-nm node for low stand-by power (LSTP) application, external parasitic resistance was reduced to 140 (NMOS) and 350 (PMOS) Ω µm. Our results show that ρc is an important component of parasitic resistance in terms of improving device performance of UTSOI MOSFETs.

Impact of Gate Metal-Induced Stress on Performance Modulation in Gate-Last Metal–Oxide–Semiconductor Field-Effect Transistors

We have proposed guiding principle of material selection of electrode/dielectric combination for MIM DRAM capacitors by theoretically taking the tunneling barrier height into account. Accordingly, we found that phase-controlled HfO2 (HfAlO) with TiN electrode is promising. TiN/HfAlO/TiN MIM capacitors with an ultra-thin Al2O3 on the bottom TiN electrode were fabricated and an EOT of 0.7 nm with a leakage current of 80 nA/cm2 was successfully achieved.

Metal Schottky Source/Drain Technology for Ultrathin Silicon-on-Thin-Box Metal Oxide Semiconductor Field Effect Transistors

We investigated the controversial effective workfunction and electron mobility of TiN/HfSiON devices by intentionally adding MgO or La2O3 into HfSiON and by changing the material on TiN or the TiN thickness. As a result, we found a close relationship between the electron mobility at low effective field and the flatband voltage. This relationship is explained on the basis of the fixed charge in HfSiON and its neutralization. The intrinsic workfunction of TiN/HfSiON without charge is determined to be 4.3 eV from the flatband voltage when the electron mobility at low effective field is the highest.