Armin Fischer

Experimental data and statistical models for bimodal EM failures

The correct model for the electromigration failure distribution is a key issue in reliability methodology. Usually, the failure times of a sample are fitted by a single log-normal distribution. However, in some cases relevant deviations can be found. In this paper two types of non-log-normal distributions observed on via-line structures are discussed. They can be modeled by two types of bimodal distributions, each composed of two log-normal distributions. Both models consider different failure mechanisms within the sample or specimen. Experimental data sets coinciding with either model will be presented. The physical failure analysis confirms the model assumptions and supports the bimodal distribution concept.

Using the temperature coefficient of the resistance (TCR) as early reliability indicator for stressvoiding risks in Cu interconnects

Comprehensive investigations were carried out to study the correlation between the temperature coefficient of resistance (TCR) and both the microstructure and the stressvoiding behavior of copper dual damascene (DD) interconnects. TCR values have been investigated with regard to median grain size and crystal lattice defects. For narrow submicron lines the TCR was found to decrease exponentially with line width as the grains become smaller. For wide lines the value decreases with the plating thickness since the median grain size in thinner films becomes smaller as well. A change of grain size was observed in samples subjected to different post-plating anneal temperatures. Samples treated at lower temperature contain smaller grains resulting in reduced TCR values and are affected by stress-induced voiding as a consequence of vacancy generation due to recrystallization and grain growth. In contrast, no stressvoiding was observed in the case of high temperature anneals, where the samples show considerable larger grains and thus higher TCR values. A clear correlation was found between lattice defects, the measured TCR and stressvoiding behavior. Samples with a large number of crystal defects are affected by stressvoids due to the recovery of the defects. They show significantly smaller TCR values compared to samples with an intact crystal lattice which are not susceptible to stress-induced voiding. The results demonstrate the capability of TCR measurements to reveal microstructural differences such as median grain size or the density of crystal defects, as the result of different interconnect geometries or process-related influences. The measurement of the temperature coefficient of resistance is not only a powerful method to characterize the microstructural properties of copper interconnects but also shows potential as an early indicator of stressvoiding risks, e.g. during in-line monitoring.

Process optimization-the key to obtain highly reliable Cu interconnects

In this paper, we describe electromigration and stressvoiding mechanism in copper interconnects.

Modeling bimodal electromigration failure distributions

Abstract One of the major tasks in reliability methodology is the correct modeling of electromigration failure distributions. Usually the failures within a sample of test devices are caused by a single physical failure mechanism and the resulting failure distribution can be tight-fitted by a single log-normal distribution. However, it is possible that several failure mechanisms are active within the sample or even one specimen implying multimodal failure distributions. In this paper bimodal log-normal distributions will be discussed, which show two distinct branches as a consequence of two failure mechanisms. In order to describe these failure distributions we use two models – the superposition model and the weak-link model. Both are composed of two log-normal distributions and consider different failure scenarios. We show that they are special cases of one general bimodal model. For each model, coinciding experimental data sets will be presented, which were observed on different via-line structures. The physical failure analysis confirms the model assumptions and supports the bimodal distribution concept.

Stress-induced voiding in aluminum and copper interconnects

Stress-induced voiding (SIV) is a serious reliability problem in metal interconnects. For aluminum a phenomenological model was developed which allows the extrapolation of metallization life times from stress conditions to operation conditions of the integrated circuit. Resistance drift measurements during high-temperature storage (HTS) on wafer-level have been performed and the experimental data could be fitted with that model. The influences of different parameters such as line width, metal level, thermal anneals of certain metal levels during processing and the deposition temperature of the interlevel dielectric material on the SIV behavior are discussed. The SIV behavior of copper dual damascene metallizations has been investigated on via line structures. A linear resistance drift during high-temperature storage has been observed. This is in contrast to aluminum, where a non-linear behavior was found. Failure analysis showed voids inside the via and not in the metal line as it has been observed in aluminum. Stress simulations have been performed in order to explain this behavior. Due to the complex stress state in a copper dual damascene via the temperature dependence of SIV in copper is different from that of aluminum.

TDDB robustness of highly dense 65NM BEOL vertical natural capacitor with competitive area capacitance for RF and mixed-signal applications

The integration of vertical natural capacitors (VNCap) into existing backend-of-line (BEOL) stacks is an important aspect to enable radio-frequency and mixed signal features without extra mask costs. From manufacturing and reliability point of view these devices can be rather challenging since they may contain millions of vias and meters of metal interconnects. In this paper we will discuss the robustness of densely packed vertical natural capacitors against time dependent dielectric breakdown (TDDB) with respect to both intrinsic and extrinsic aspects. The intrinsic TDDB of VNCap is sensitively influenced by the design aspects that change the physical spacing within the metal pattern. A strong trade-off between area capacitance and intrinsic TDDB was observed. If the tested VNCap area is large enough, early failures were systematically detected with a certain probability. We will discuss a method that allows the modelling of an early thinning mode due to unavoidable spacing variations within the patterns. Based on this method a criterion is derived to distinguish between early fails that can still be tolerated and extrinsic defects of gross nature that are critical. Furthermore we will present observations on the influence of BEOL process aspects on intrinsic TDDB performance and extrinsic defect density such as CMP slurry and overpolish or time delay after trench etch and copper CMP.

New approaches for the assessment of stress-induced voiding in Cu interconnects

Stress-induced voiding (SIV) in copper interconnects was studied during high temperature storage (HTS). Stressvoids were observed in the Cu-line under dual-damascene (DD) vias and W-plugs, respectively. In both cases medium failure times are decreasing exponentially with increasing stress temperature. On structures with W-plugs two voiding modes with different activation energies were observed, on Cu-lines with DD-vias a monomodal behavior only. Design features such as line width, length or via-to-line overlap have a strong influence on SIV. Based on the presented data a method is proposed that allows the approximation of SIV-limited lifetime under operation conditions.

Electromigration behavior of interconnects between chip and board for embedded wafer level ball grid array (eWLB)

The electromigration (EM) behavior at critical interfaces of copper redistribution layers (RDL) used in an embedded wafer level ball grid array (eWLB) package has been studied. The EM failure times at the chip pad and solder ball interface were measured for various design configurations such as via diameter, additional under bump metallization or RDL shapes for different current directions. The maxium currents at the chip pad interface are limited by voiding in the relatively thin aluminum pad underneath the copper RDL via followed by liner punch-through during downstream stress. The corresponding activation energies (Ea) and current density exponents (n) are the typical ones found for polycrystalline aluminum lines. In contrast, the solder/RDL interface is critical when operated in upstream direction. The voiding is driven by copper migration causing accelerated Cu-consumption at the transition between RDL feeding line and solder ball, which is the location with the highest current density, defined Cu/Cu3Sn intermetallic compound (IMC) boundaries and pre-existing Kirkendall voids. For the solder interface, a typical Ea-value around 1.0 eV was found in combination with a n-value far above 2.0 which we associate with an additional diffusional contribution to the overall migration rate in Blacks equation rather than Joule heating.