Philipp Riess

Reliability aspects of gate oxide under ESD pulse stress

Power law time-to-breakdown voltage acceleration is investigated down to ultra-thin oxides (1.1 nm) in the ESD regime in inversion and accumulation. Breakdown modes, oxide degradation and device drifts under ESD like stress are discussed as function of the oxide thickness. The consequent impacts on the ESD design window are presented.

ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-/spl mu/m CMOS technology

Historically, the failure mode of the nMOS/lateral n-p-n (L/sub npn/) bipolar junction transistor (BJT) due to electrostatic discharge (ESD) is source-to-drain filamentation, as the temperature exceeds the melting temperature of silicon. However, as the gate-oxide thickness shrinks, the ESD failure changes over to oxide breakdown. In this paper, transmission line pulse (TLP) testing is combined with measurements of various leakage currents and numerical simulations of the electric field to examine the failure mode of an advanced 0.1-/spl mu/m CMOS technology, which is shown to be through gate-oxide breakdown. It is also shown by I/sub D/-V/sub G/ and I/sub G/-V/sub G/ measurements that the application of nondestructive ESD pulses causes gradual degradation of the oxide well before failure is reached, under the (leakage current) failure criteria used. Finally, the latent effects of stress-induced oxide degradation on the failure current I/sub f/ of the nMOS/L/sub npn/ are studied, and it is shown that as the device ages from an oxide perspective, its ESD protection capabilities decrease.

Electrostatic discharge induced oxide breakdown characterization in a 0.1 /spl mu/m CMOS technology

Historically, the failure mode of the NMOS/lateral NPN (Lnpn) due to electrostatic discharge (ESD) is source-to-drain filamentation as the temperature exceeds the melting temperature of silicon. However, as the oxide thickness shrinks, the ESD failure is instead due to oxide breakdown. In this paper, transmission line pulse (TLP) testing of the NMOS/Lnpn device is used to characterize the failure mode for a 0.1 /spl mu/m NMOS. The channel length and non-silicided source contact-to-gate spacing (SCG) are the main parameters in determining ESD protection capability. Using Id-Vg measurements, we show how oxide degradation before failure is detected with the leakage current failure criteria used. The latent effects of oxide degradation on the second breakdown current (It2) of the NMOS/Lnpn are identified. As the ultra-thin oxide (15 A) device ages from an oxide perspective, its ESD protection capabilities decrease.

Dielectric absorption of low-k materials: extraction, modelling and influence on SAR ADCs

Low-k dielectrics will be required to continue miniaturisation of integrated circuits beyond the 90 nm node. The integration of these advanced materials results in significant reduction of signal delay and power dissipation compared to conventional silicon dioxide. As the technology continues to advance, the implementation of low-k dielectrics for the 65 nm node (Luo, et al., 2004) causes also problems, when using backend of line (BEOL) capacitors in mixed signal circuits. Especially the dielectric absorption effect increases dramatically. It limits the performance of capacitors and the circuits, where the capacitors are used (Zanchi, et al., 2000). A SAR ADC is a good example to show the impact of this effect. This paper presents the extraction and the modelling of the dielectric absorption effect of a low-k material as well as its influence on the resolution of a differential 16 bit SAR ADC