Arnaud Carer

Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks

To design autonomous wireless sensor networks (WSNs) with a theoretical infinite lifetime, energy harvesting (EH) techniques have been recently considered as promising approaches. Ambient sources can provide everlasting additional energy for WSN nodes and exclude their dependence on battery. In this article, an efficient energy harvesting system which is compatible with various environmental sources, such as light, heat, or wind energy, is proposed. Our platform takes advantage of double-level capacitors not only to prolong system lifetime but also to enable robust booting from the exhausting energy of the system. Simulations and experiments show that our multiple-energy-sources converter (MESC) can achive booting time in order of seconds. Although capacitors have virtual recharge cycles, they suffer higher leakage compared to rechargeable batteries. Increasing their size can decrease the system performance due to leakage energy. Therefore, an energy-neutral design framework providing a methodology to determine the minimum size of those storage devices satisfying energy-neutral operation (ENO) and maximizing system quality-of-service (QoS) in EH nodes, when using a given energy source, is proposed. Experiments validating this framework are performed on a real WSN platform with both photovoltaic cells and thermal generators in an indoor environment. Moreover, simulations on OMNET++ show that the energy storage optimized from our design framework is utilized up to 93.86%.

An FPGA Software Defined Radio Platform with a High-Level Synthesis Design Flow

Software defined radio (SDR) opens a new door to future Internet of Things with higher degree of designing flexibility in context of wireless system development. Prototyping a remote implementation of wireless protocols on a hardware over the web requires a highly versatile software radio platform along with laid-back designing tools. To this aim, an FPGA-based SDR scheme has been proposed combining Virtex-6 Perseus 6010 platform capabilities and a design flow based on High-Level Synthesis (HLS) tools. A full IEEE 802.15.4 (ZigBee) physical layer has been implemented on the proposed platform from a C-language dataflow specification. All the results have been analyzed to lead to a fair comparison between different design flows. Although the proposed SDR has some designing issues, it shows a noticeable designing potentiality to flexible prototyping of future wireless systems.

Real-time on-demand multi-hop audio streaming with low-resource sensor motes

The European EAR-IT project addresses “real-life” experimentations of intelligent acoustic for supporting high societal value applications in a large-scale smart environment. For instance a city emergency center can request on-demand acoustic data samples for surveillance purposes and management of emergencies. In this paper, we will present experimentations on streaming encoded acoustic on the SmartSantander large scale test-bed. We will present the various audio hardware that were developed to meet the constraints of audio capture and transmission with low-resources devices. We will highlight the main sources of delays and will show how multi-hop streaming of acoustic data can be achieved by carefully taking into account these performance limitations with appropriate audio aggregation techniques.

First experimental demonstration of real-time orchestration in a Multi-head metro network

We present for the first time the experimental demonstration of a Real-Time control-plane on the Multi-hEad sub-wavElength swiTching (MEET), Metro architecture. The key control assets are calculated and provided to the edge nodes in a form of grant files. These grant files eliminate the contention possibility at source nodes and destinations, thus they offer a lossless passive optical grooming and multiplexing/demultiplexing at the intermediate nodes. The experimental results validate the control plane structure designed based on a deterministic operating system well scalable for a regional metro network.

A coarse-grain reconfigurable hardware architecture for RVC-CAL-based design

MPEG Reconfigurable Video Coding project aims at providing more flexible and easier solutions to specify video coders and decoders. Many contributions are devoted to the RVC-CAL language, the standard description language. There are also contributions about the general framework of this new model of video coding, and many CAL descriptions for video algorithms. However, RVC compliant implementations have been only studied next to code generation which does not take advantage of major characteristics of CAL networks as they are dataflow graphs. Consequently, there are no dedicated architectures that are inherently bound to the CAL language. The objective of this article is to present preliminary work about the design of a co-processor based architecture. The co-processor is a reconfigurable architecture that uses CAL network features and proposes a dynamic memory allocation system, which improves the communication between the processes that are implemented, and enables to allocate minimum memory.

Experimental demonstration of real time receiver for frequency division multiple access PON

First real time implementation of a 1Gbps FDM receiver in FPGA for an ONU and OLT receivers without data-aided. This demonstrate, for US and DS, an optical budget up to 34 dB for a BER<;10-3.