Antoine Courtay

High-Level Interconnect Delay and Power Estimation

It is now well admitted that interconnects introduce delays and consume power and chip resources. To deal with these problems, some studies have been done on performance optimization. However, as the results presented in this paper show, such techniques are not based on good criteria for interconnect performance optimizations. We have, therefore, developed a high-level estimation tool based on transistor-level characteristics, which provides fast and accurate figures for both time and power consumption. These results allowed us to create a new interconnect consumption model and also to determine new key issues that have to be taken into account for future performance optimizations.

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform

The FlexTiles Platform has been developed within a Seventh Framework Programme project which is co-funded by the European Union with ten participants of five countries. It aims to create a self-adaptive heterogeneous many-core architecture which is able to dynamically manage load balancing, power consumption and faulty modules. Its focus is to make the architecture efficient and to keep programming effort low. Therefore, the concept contains a dedicated automated tool-flow for creating both the hardware and the software, a simulation platform that can execute the same binaries as the FPGA prototype and a virtualization layer to manage the final heterogeneous many-core architecture for run-time adaptability. With this approach software development productivity can be increased and thus, the time-to-market and development costs can be decreased. In this paper we present the FlexTiles Development Platform with a many-core architecture demonstration. The steps to implement, validate and integrate two use-cases are discussed.

Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses

Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data coding for interconnect power and timing optimization has been introduced. In todays SoCs these techniques are not efficient anymore due to their codec complexity or to their unrealistic experimentations. Based on some realistic observations on interconnect delay and power estimation, the spatial switching technique [1] is proposed. It allows the reduction of delay and power consumption (including extra power consumption due to codecs) for on-chip buses. The concept of the technique is to detect all cross-transitions on adjacent wires and to decide if the adjacent wires are exchanged or not. Results show the spatial switching efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 5-mm bus and more if buses are longer.

New directions in interconnect performance optimization

It is now admitted that interconnects represent a bottleneck for delay, power consumption and area on chips. To face these problems some works have been realized around performance optimizations. However results, presented in this paper, show that optimization techniques do not always face good criteria for interconnect performance optimizations. We therefore have developed a high-level estimation tool based on transistor-level characterizations, which provides users fast and precise results for time and power consumption estimation. Estimation results allowed us to determine a new interconnect consumption model and also enabled to find some new key issues that have to be pointed out for future performance optimizations.

Design flow and run-time management for compressed FPGA configurations

The aim of partially and dynamically reconfigurable hardware is to provide an increased flexibility through the load of multiple applications on the same reconfigurable fabric at the same time. However, a configuration bit-stream loaded at runtime should be created offline for each task of the application. Moreover, modern applications use a lot of specialized hardware blocks to perform complex operations, which tends to cancel the “single bit-stream for a single application” paradigm, as the logic content for different locations of the reconfigurable fabric may be different. In this paper we propose a design flow for generating compressed configuration bit-streams abstracted from their final position on the logic fabric. Those configurations will then be decoded and finalized in real-time and at run-time by a dedicated reconfiguration controller to be placed at a given physical location. Our experiments show that densely routed applications gain the most with a compression factor of more than 2× using the finest cluster size, but coarser coding can be implemented to achieve a compression factor up to 10×.

Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture

Dynamically and partially reconfigurable architectures, like FPGAs, have increasingly become heterogeneous with DSP, RAM and communication interface blocks. However, in most of online FPGA task placement approaches, the FPGA is modeled as a homogeneous architecture. In this work, we propose a heuristic which focus on the online task placement problem on a multi-context, dynamically and partially heterogeneous reconfigurable architecture. Configuration Prefetching and Anti-fragmentation well known techniques are combined with the Place Reservation technique in order to improve resource usage capacity. Compared to a placement without reservation, our approach improves, on average, by 33% the number of placed tasks and by 46% the resource utilization rate.

Spatial Switching data coding technique analysis and improvements for interconnect power consumption optimization

It is currently an acknowledged fact that interconnects introduce delays and consume power and chip resources. To deal with these issues, data coding for interconnect power and timing optimization has been introduced. In todays Systems On Chip, some of these techniques are no longer efficient due to their codec complexity or to their experimentations that are not realistic anymore. Based on some realistic observations on interconnect delay and power estimation, previous works have introduced the Spatial Switching technique, which allows the reduction of delay and power consumption for on-chip buses. This paper deals with some Spatial Switching improvements and also explains how to obtain automatically the best results in terms of power consumption reduction with the Spatial Switching technique by using the Interconnect Explorer tool.

A convolutional code for on-chip interconnect Crosstalk Reduction

Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data-coding for interconnect power and timing optimization is a promising method. Based on some realistic observations on interconnect delay and power estimation, a new data-coding technique called “Convolutional Encoder for Crosstalk Reduction” (CECR) is proposed. It allows the reduction of delay, power consumption (including extra power consumption due to codecs) and noise for on-chip buses. The concept of the technique is to reduce the switching activity to its minimum considering the transmission of data on the encoded wires. Results show the technique efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 10 mm bus in the 65 nm technology and more if buses are longer. It also allows the acceleration of the data propagation of 20% and the reduction of the overall worst noise case transitions of 51%.