Arnaud Garnier

Underfilling techniques comparison in 3D CtW stacking approach

Die stacking in 3D integration increasingly deals with smaller soldered joints on flip chips which have to meet reliability requirements especially thermal cycling, vibrations, shocks. Adding an underfill between stacked chips is a solution to improve the structural integrity of those joints. In this work, different underfilling techniques are compared in chip to wafer (CtW) approach: one capillary underfill (CUF) and three pre-applied underfills (PAUF) including one non conductive paste (NCP) and two wafer level underfills (WLUF). These underfilling solutions are assessed using a test vehicle including daisy chains for electrical tests. Preconditioning and temperature cycling tests were carried out to monitor reliability. CUF and NCP enable to get good interconnections electrical resistance after 500 cycles. On the other side, WLUF process currently appears to be harder to implement because of lack of reproducibility and polymer entrapment at the bonding interface, preventing a reliable electrical contact. Advantages and drawbacks of each underfilling processes are also discussed regarding for instance maturity, easiness of process, throughput, creeping risks, entrapment risks, fine pitch and fine gap compatibility. It is obvious that PAUF are inevitable for 3D high density involving gap between stacked chips. However, related process speed is still low for PAUF. Further work on products and processes is thus needed to get reliability performances and cost-effectiveness suitable with high volume manufacturing.

3D advanced integration technology for heterogeneous systems

3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, μ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuits description.

Investigation of copper-tin transient liquid phase bonding reliability for 3D integration

Copper tin transient liquid phase bonding reliability was investigated with different setups including CuSn to Cu and CuSn to CuSn bonding. Additionally, a thermal treatment just after CuSn electrodeposition (ECD) was compared to the classical configuration. Thermal cycling test (TCT) was achieved with electrical and mechanical tests carried out before and after TCT to discriminate the setups. Before TCT, each configuration has very good electrical properties in terms of yield (>90%) and Kelvin resistance. Shear tests show good mechanical properties in all tested cases as well. However, SEM images reveal different kinds and densities of voids. Kirkendall voids are localized at the Cu/Cu3Sn interface. Smaller voids are visible at the initial bonding interface in the case of CuSn to Cu bonding. After TCT, configurations are well discriminated. CuSn to Cu configuration exhibits the worst properties: electrical yield drops at nearly 30% and shear strength loses 80% of its initial value. On the other hand, CuSn to CuSn configuration and configuration including the post ECD thermal treatment keep correct electrical yield above 80%, and has shear strength loss in the range of 30 to 50%. SEM images after TCT reveals crack localization mainly through Kirkendall voids planes either on top side or on bottom side. Hypotheses regarding these results are discussed.

ITAC: A complete 3D integration test platform

System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of “Integrated Technological and Application Circuits” for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 μm diameter 20 μm pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test.

RF Characterization and Modeling of 10 µm Fine-Pitch Cu-Pillar on a High Density Silicon Interposer

This work aims at providing a RLCG modeling ofthe 10 µm fine-pitch microbump type interconnects in the 100 MHz-40 GHz frequency band based on characterization approach. RF measurements are performed on two-port test structures within a short-loop with chip to wafer assembly using the fine pitch 10 µm Cu-pillar on a 10 Ohm.cm substrate resistivity silicon interposer. Accuracy is obtained thanks to a coplanar transmission line using 44 Cu-pillar transitions. To the author knowledge, it is the first time that RLCG modeling of fine-pitch Cu-pillar is extracted from experimental results. Another goal of this work is to get a better understanding of the main physical effects over a wide frequency range, especially concerning the key parameter of fine pitch Cu-pillar, i.e. the resistance. Finally, analysis based on the proposed RLCG modeling are performed to optimize over frequency the resistive interposer-to-chip link thanks to process modifications mitigating high frequency parasitic effects.

Quality and Reliability Assessment of Cu Pillar Bumps for Fine Pitch Applications

This paper presents the relations between processing, microstructure and mechanical reliability of copper pillar bumps (CuPi). Two sets of samples were manufactured: Cu/SnAg and Cu/Ni/SnAg with diameters between 15 and 20 µm. From the microstructure point of view: at these dimensions and for simulated reflows, up to 5, intermetallic compounds (IMC) follow a classical power law with a time exponent value between 1/3 and 1/2 indicating the interfacial IMC growth is grain boundary/volume diffusion-controlled. Adding a Ni layer limits micro-voids and IMC growth (~2-3 µm wo. Ni vs. ~1 µm w. Ni). From the mechanical/reliability point of view: the more reflow, the tougher the Cu pillar bumps. With 5 reflows, the pillar bump is a minima 74 % tougher for a Cu/SnAg one and 19 % for a Cu/Ni/SnAg one. At the investigated shear heights, the fracture is always in the solder without any apparent impact of IMC growth.

Electrical Performance of High Density 10 µm Diameter 20 µm Pitch Cu-Pillar with Chip to Wafer Assembly

Microbump-based interconnects with 20 µm pitch have been fabricated on 300 mm wafers using industrial tools. Good processes control enables to get narrow standard deviations for the microbumps height (0.2 µm) and diameter (0.4 µm). Assembly was studied with chip to wafer (CtW) test vehicles by either mass reflow (MR) or thermo-compression (TC) with or without non-conductive paste (NCP). MR and TC processes result in suitable CtW alignments without significant defects at bonding interface. TC NCP assembly suffers from larger misalignment and underfill entrapment, reducing top to bottom bonding section. Consequently, unit electrical resistance is lower for MR and TC processes with ~25 m ascribed to pure vertical link, than for TC NCP process exhibiting ~50 m vertical link with larger standard deviation (15 m versus 2 m). Intermetallic compounds have been studied and Ni3Sn4 proves to be the main contributor for electrical resistance in our configuration where SnAg is sandwiched between 2 Ni layers. Electrical yield measured on daisy chains is very good (close to or higher than 90%) for MR or TC, even on more than 20,000 interconnects. For TC NCP, electrical yield remains to be improved, particularly on large daisy chains. Finally, an original electrical test has been designed and successfully implemented to characterize top to bottom misalignment. These results are promising for future high performance computing products that would require 20 µm pitch microbumps.

Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement

This paper is dedicated to the full integration of innovative silicon-based material for Wafer-Level molding of silicon interposer wafers. This technology can be used in the frame of silicon packages where the silicon interposer is either reported on P-BGA or directly assembled on board. Interest of such material, is the rapid Wafer-Level lamination process and die planarization which can facilitate interposer realization. In a first part of the article, we have evaluated the compatibility of this material with the whole interposer flow by having a focus on filling capacities as well as induced deformation on 300mm wafers. Secondly, we have generated electrical test vehicles in order to verify the impact of such material on environmental and mechanical reliability.

Reliability of die to wafer bonding using copper-tin interconnections

One major step for 3D integration is the die stacking which has to meet mechanical and electrical requirements. Transient Liquid Phase bonding is studied because it is suitable with high interconnection density and also multiple stacking. For this study, top and bottom wafers including redistribution layers were electroplated with CuSn and Cu respectively. Die to wafer bonding was carried out at 250 °C in neutral atmosphere. Capillary underfill was added in some cases to check its influence. Interconnections quality was then assessed. Electrical tests were carried out using daisy chains. Shear tests enabled to check mechanical strength and failure location. Finally, cross sectional scanning electron microscopy and energy dispersive X-ray spectrometry allowed identifying metallurgical phases and potential defects. These characterizations were achieved before and after aging. This aging consisted either in thermal cycle test (TCT: 500 cycles between −40 °C and 125 °C with 10min soak time) or high temperatur...