Jean Michailos

Color filters including infrared cut-off integrated on CMOS image sensor

A color image was taken with a CMOS image sensor without any infrared cut-off filter, using red, green and blue metal/dielectric filters arranged in Bayer pattern with 1.75 µm pixel pitch. The three colors were obtained by a thickness variation of only two layers in the 7-layer stack, with a technological process including four photolithography levels. The thickness of the filter stack was only half of the traditional color resists, potentially enabling a reduction of optical crosstalk for smaller pixels. Both color errors and signal to noise ratio derived from optimized spectral responses are expected to be similar to color resists associated with infrared filter.

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links

By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4x4x2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.

3D integration demonstration of a wireless product with design partitioning

3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customers interest by showing him evaluations and results on real industrial applications. Heterogeneous integration and the possibility to partition different functions of a product in separate layers is one of the advantages of 3D integration. In this paper, product partitioning with TSV and 3D integration is demonstrated without inducing any impact on final product functionality and on early package level reliability tests.

New challenges and opportunities for 3D integrations

From low density 3D integrations embedding Via Last Through Silicon Vias (TSV) to high densities hybrid bonding or 3D VSLI CoolCubeTM solutions, a multitude of new product opportunities is now envisioned. An overview of existing emerging 3D integrations is provided covering Image sensors, Photonics, MEMS, Wide I/O memories and Silicon Interposers for advanced logics. Associated key challenges and developments are highlighted focusing on 3D platform performance assessment.

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

This paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness.

A

Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1:8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers.

4 \times 4 \times 2

This paper presents a comparison between electrical measurements, which are carried out with embedded in-situ sensors, and thermal numerical simulations. The objectives of this study are firstly to calibrate the Finite Element model by comparing the measurement results with those from simulations through a Design Of Experiments (DOE), and then to provide thermal recommendations on the studied parameters thanks to the calibrated numerical model. The primary objective of the DOE is to quantify the sensitivity of modeling parameters. Results show a strong influence of the silicon thickness, the convective heat transfer coefficient of the bottom surface, the thickness of the thermal insulation and the position of the hot spots relative to the sensors. The boundary conditions, particularly the heat transfer coefficient are also identified as significant parameters. Once the main factor set determined, the second objective of this study is to weight quantitatively the influence of key parameters. Finally, by providing a numerical and experimental comparison, this paper provides validated values of boundary conditions to be applied in the numerical simulations. These are considered to be the most difficult to obtain, while they have a huge influence on the simulation results, and this work allows to provide reliable thermal recommendations on designs to manage self-heating challenges.

Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links

The 3D IC technology has attracted much interest in the recent past as a mean to efficiently improve performance and miniaturization of electronic integrated circuits (IC) [1]. The integration is based on three dimensional (3D) die stacking, connected thanks to Through Silicon Vias (TSV), μcopper pillars and large copper pillars. Although this approach offers several advantages in terms of electric features, the thermal management is widely identified as one of the key challenges [2]. The purpose of this study is to present a numerical model based on finite elements, to be calibrated and validated by experimental means (i.e. electrical in-situ and thermal IR measurements). In this paper, a presentation of our test chip (stacking, heaters and embedded sensors), the impact of various geometric parameters, the behavior of TSV around heated areas, and thermal properties of materials in the 3D stack-based will be presented. Our numerical model is composed of two chips stacked on a BGA. We use homogenized properties of TSV, Cu-Pillars (CP), μCP and BEOL. The best combination of geometrical (diameter, pitch) and technological (SiO2 and Silicium thickness, underfill properties) parameters in terms of thermal dissipation is extracted through design of experiments. We aim to know the internal thermal behavior despite the strong influence of poorly known boundary conditions. Finally, by proposing a whole numerical and experimental approach, this paper brings insights for early phase development of 3D ICs on self heating questions.

Thermal correlation between measurements and FEM simulations in 3D ICs

System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of “Integrated Technological and Application Circuits” for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 μm diameter 20 μm pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test.

Thermal behavior of stack-based 3D ICs

We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.