Stephan Niel

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology

This paper describes different solutions to decrease dynamic consumption of circuits processed on an embedded non-volatile memories CMOS 80 nm technology. Up to 25 % in dynamic power reduction is demonstrated without degrading performances and static leakages of devices and above all, with full DMR compliancy. Ring oscillator designs are used to estimate the dynamic power gain, comparing new development process (B) to reference process (A) currently in use in manufacturing.

Experimental study to push the Flash floating gate memories toward low energy applications

The problem of energy saving has today a relevant importance, concerning in particular all the portable devices as smart phone, tablet PC, smart card and so on [1]. In order to improve the features of these products, particular attention is paid to energy consumption of Flash cells in memory arrays. In this work we investigated the Flash floating gate (FG) dynamic behavior during the channel hot electron (CHE) programming operation. After this, we propose a solution to optimize the energy consumption. The samples studied in this experimental work are Flash floating gate memory cells (embedded NOR flash process). The ONO inter-poly dielectric stack has an equivalent thickness of 14nm, while the tunnel oxide of 9.5nm is grown on a p-type silicon substrate. We evaluated the variation effect of two important technological parameters: channel doping dose (CDD) and lightly doped drain (LDD) energy implantation.

Stress Development and Relaxation during Reaction of a Cobalt Film with a Silicon Substrate

Thin metal films react with silicon substrates to form various metal silicides. The sequence and kinetics of phase formation are still an area of intense research. Comparatively much less work has been done on the issue of stress development caused by the appearance of these new phases. A detailed review of the subject has been done ten years ago. We present here recent results obtained on Pd-Si, Co-Si, Ni-Si and discuss them in the light of what is known today on the elastic and plastic properties of thin films. A simple model published by S. - L. Zhang and F. M. d’Heurle takes into account the simultaneous stress formation due to the reaction and the relaxation of these stresses. It provides a qualitatively satisfying picture of stress evolution at least for the first phase which forms. The model relies on two basic elements: 1) stress formation due to the formation of a new phase, and 2) the stress relaxation mechanism at work in the growing silicide film. The sign of the stress can be understood from the variation in volume that occurs at the growing interface(s). The stress relaxation mechanisms at work in a growing film are complex. They are highly dependent on the microstructure (as we have shown when comparing Pd/Si(001) and Pd/Si (111)) but should be also highly size dependent (e.g. dislocation glide is more difficult in small scale structures). Inhomogeneous plastic relaxation in polycrystalline silicide films may be an important issue.

Radiation tolerance of npn bipolar technology with 30 GHz Ft

The tolerance to both ionizing dose and displacement damage of a Quasi-Self Aligned (QSA) single polysilicon emitter bipolar technology fabricated with a 0.35 /spl mu/m design rules CMOS is presented. In this work we explore the effect of dose rate, high dose level irradiation and elevated temperature irradiation on the electrical performance of single polysilicon bipolar transistors. The different results are discussed and comparison with previous are presented to place the technology with respect to others.

A new non-volatile memory cell based on the flash architecture for embedded low energy applications: ATW (Asymmetrical Tunnel Window)

In this paper we propose a new non-volatile charge trap memory architecture implemented on 200mm wafer in 90nm technology node. The aim of this work is to investigate an alternative and scalable solution for embedded low energy applications. The Asymmetrical Tunnel Window (ATW) memory cell has been developed in order to improve the programming operation during a hot carrier injection. The main property of this device is the presence of an asymmetrical tunnel oxide thickness along the channel. This characteristics enables an improvement in terms of current consumption and injection efficiency with respect to the standard Flash floating gate memory cell. In this work we describe the fabrication process of ATW memory cell and, using a commercial TCAD simulator and experimental results, we demonstrate the good functioning of our device thanks to the increased control gate/floating gate (CG/FG) coupling factor. To conclude we confirm the reliability performances with the endurance experiments up to 100k cycles.

The Design and Fabrication of 0.35 µm Single-Polysilicon Self-Aligned Bipolar Transistors

Two innovative process technologies are introduced to overcome problems related to the downscaling of single-polysilicon self-aligned bipolar transistors. First, the use of a selective silicon deposition step before Ti salicidation of the structure is shown to improve TiSi2 formation on narrow As-doped polysilicon emitters. At the same time, the elevation of the extrinsic base regions around the emitter causes a significant reduction of peripheral electron recombination effects. Second, the implantation of the intrinsic base at a large tilt angle (LATIB) is demonstrated to suppress emitter-to-collector punchthrough along the isolation edges. The first 0.35 µm single-polysilicon self-aligned bipolar transistors fabricated using a 200 mm complementary metal oxide semiconductor (CMOS) derived bipolar process integrating these novel process technologies are described.

Dynamic current reduction of CMOS digital circuits through design and process optimization

This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.

Optimization of the ATW Non-Volatile Memory for Connected Smart Objects

The development of new wireless devices is growing up, driven by the market of connected things for many applications: communications, cloud and health. In this scenario the current consumption of memory devices plays a key role. To save the battery of these devices, we need to develop the components that consume less and less. In this paper we propose to improve the performances of an original architecture of nonvolatile memory cell: the Asymmetrical Tunnel Window (ATW) cell. We compare here the standard Flash floating gate memory cell with the new proposed device, with an accurate experimental investigation of programming window and energy consumption. Moreover we optimized the ATW cell architecture by modifying the ratio of oxides lengths and thicknesses. Finally, we experimentally demonstrate an improvement of 4 times on the programming efficiency with respect the standard memory.

NMOS drive current enhancement by reducing mechanical stress induced by Shallow Trench Isolation

This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transistors used in analog and digital applications is 5% higher due to the reduction in the STI-induced, compressive stress in the channel. The polysilicon wall could be added automatically in digital standard cells during cad to mask operation without increasing the size of the cells. Finally, the speed frequency of CMOS inverter ring oscillators designed with low-voltage MOSFETs used in digital standard cells is increased by 6% when a polysilicon wall is added around NMOS transistors. Moreover, the static current of ring oscillators remains unchanged.

A Dual-Gate Memory Cell with Two Inter-Poly Oxides

A new dual-gate memory cell with two different inter-poly oxides is presented in this paper. This cell allows high density memory application and a cell programming only with the dual-gate without high bias on drain or source compared to standard electrical erasable and programmable read-only memory (EEPROM). Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 48%. The specificity is to use a dual-gate to program the cell with two different ways of charge injection and perform the memory operations without high bias on drain and also without select transistor. Thus this cell can be shrunk more easily and its lifetime can be improved because the band to band tunneling stress due to high drain potential is eliminated. Moreover, this dual-gate cell can become an adjustable threshold voltage transistor.