Jean-Michel Mirabel

A new floating gate compact model applied to flash memory cell

Abstract The aim of this work is to present a method developed to simulate the direct current and transient properties of the floating gate memories. This method includes metal oxide semi-conductor charge neutrality, charges stored into the floating gate, injection currents and metal oxide semi-conductor field effects transistor characteristics to determine the surface potential variation along the channel, the floating gate potential and as a result the drain current and the threshold voltage. The resulting model was implemented in a common circuit simulator, Eldo, and used to study the flash memory writing/erasing operations. Channel hot electron injection and classical Fowler–Nordheim currents are used respectively to program and to erase this kind of memory. The simulator validation is obtained by comparing transient threshold voltage measurements performed on 0.15 μm devices with simulations.

EEPROM Compact Model with SILC Simulation Capability

The objective of this paper is to present a EEPROM compact model suitable for SILC simulation. The SILC module allows simulating the retention capability of the cell after stress. Test chip array distribution and standard tunnel capacitor are used to extract the SILC module parameters. Thus the extraction procedure is detailed. The description of the complete model is presented. A simulation example is given and validated versus measurements.

EEPROM cell design: paradoxical choice of the coupling ratio

Generally the design of the memory cell, as an electrically erasable programmable read-only memory, is based on the calculation of coupling ratio. This step is fundamental because it determines cell performances. Practically designers use the maximum coupling ratio to decrease the necessary supply voltage. Despite lower voltage, we show in this paper that this approach induces a paradoxical increase of electric field across tunnel oxide which is directly related to the lifetime of the cell. Using simulations, we demonstrate that the optimum coupling ratio depends on the best compromise between a smaller supply voltage and the cell lifetime.

Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect

A model for static and transient simulations of an electrically erasable programmable read only memory cell has been developed. This physical compact model is based on charge sheet approach which is able to describe the complete electrical behavior of the cell. In this model, we have introduced the dependence of the tunneling capacitance as a function of the voltage across the tunnel oxide and the floating gate depletion effect. This model has been successfully implemented in common circuit simulators and used for the study of the write/erase operations in a memory cell. The simulations compared to the experimental results are in good agreement.

A 0.18 /spl mu/m flash source side erasing improvement

The aim of this work is to present two solutions developed to optimize Flash cell erasing time. These solutions have been proposed with our flash simulator based on Pao and Sah approach. This model was implemented in a common circuit simulator, Eldo, and used to study the Flash memory writing/erasing operations. Thank to simulations, we have proposed two solutions to increase injection efficiency of the cell during erasing operation. The first solution is based on signal optimization and the second on a simple process modification during SAS etching. These two solutions have been validated with ST-Microelectronics Flash technologies.

A Dual-Gate Memory Cell with Two Inter-Poly Oxides

A new dual-gate memory cell with two different inter-poly oxides is presented in this paper. This cell allows high density memory application and a cell programming only with the dual-gate without high bias on drain or source compared to standard electrical erasable and programmable read-only memory (EEPROM). Concept has been validated in an EEPROM standard technology from STMicroelectronics and allows a cell area reduction of above 48%. The specificity is to use a dual-gate to program the cell with two different ways of charge injection and perform the memory operations without high bias on drain and also without select transistor. Thus this cell can be shrunk more easily and its lifetime can be improved because the band to band tunneling stress due to high drain potential is eliminated. Moreover, this dual-gate cell can become an adjustable threshold voltage transistor.

Investigation of a new three bits cell concept

New innovative electronics applications require larger memory capacity with decreasing memory array size. In this way, architectures implementing multi-bits or multi-level operations draw much attention because they proved to be one of the ways to reach this goal. In this paper, a Three Bits Cell concept, allowing 3 bits functionality, is investigated. This solution is obtained with multi-bits and multi-level memory combination. Such memory cell requires a perfect control of injection mechanisms. This paper presents cell design and injection mechanisms optimization. This cell is based on two floating gates architecture coupling with a middle channel implant. The erasing operation is done by Fowler-Nordheim with sharp effect (FNSE) in the floating gates. This injection needs a precise process creating a sharp edge on the floating gate. CAFM measurements showed that this sharp effect increases the tunneling electric field by a factor of 400 locally. Furthermore, a study is achieved with different doping characteristics to improve electron Band To Band Tunneling effect (eBTBT) used during writing operation. This study leads to an increase of the injection current, which is 10 times greater than a classical structure. The electrical characterizations of these mechanisms are performed to highlight the huge possibilities of this cell.