Arnd Dietrich Weber

Increase of SiC Substrate Resistance Induced by Annealing

We report here an anisotropic increase in SiC bulk resistivity by annealing at 1150 °C, and discuss the implications for SiC devices. The increase in resistivity is resistivity dependent and can be (at least) partially reversed by a subsequent anneal at higher temperature. Ideal device performance is achievable with appropriate annealing steps during device processing.

Quality Aspects for the Production of SiC Bulk Crystals

For several years the major focus of material issues in SiC substrates was laid on the reduction of macroscopic defects like polytype inclusions, low angle grain boundaries and micropipes. Since then significant improvements have been achieved and micropipe densities could be reduced to values below 1 cm-2. Nevertheless the fabrication of high quality substrates at high volume and low cost is still challenging. Therefore preconditions for reproducible process and quality control will be discussed. Since it is obvious that dislocations are the main reason for degradation in power devices the prevailing attention has also been shifted to that field of material research. Intense studies were utilized on dislocation and stacking fault formation during sublimation growth. For this reason we systematically varied crucial parameters of the crystal growth process and applied several specific characterization methods, e.g. KOH-defect-etching, electron microscopy and optical microscopy, to evaluate resulting material properties. The investigations were accompanied by failure analysis on devices of the Schottky-type. We found out that for the improvement of substrate quality emphasis has to be laid on the reduction of thermoelastic stress in the growing crystal. The results of numerical calculations enabled us to derive moderate growth conditions with reduced temperature gradients and correspondingly low defect concentration.

High Quality 100mm 4H-SiC Substrates with Low Resistivity

One of the most crucial defects for the device fabrication on silicon carbide (SiC) substrates are areas with low crystalline quality and micro-pipe clusters which can still occupy several percent of the area in commercial available 4H-substrates. These defects originate from the seed or are generated by modification changes during growth and can be easily detected under crossed polarizers. In this presentation the historic development at SiCrystal from Acheson material to wafers with 100mm diameter, state of the art micro-pipe density and excellent crystalline quality (FWHM < 20 arcsec) on whole area will be shown. Additionally the influence of carbon inclusions on surface quality and the present dislocation densities in 4H substrates will be discussed. While carbon inclusions were reduced to uncritical levels dislocation densities are still in the range of 104 cm-2. Therefore strategies for further reduction will be pointed out. Finally a resistivity limit (16 mΩcm) for stacking fault formation during annealing at 1150°C will be defined.

4H-SiC Homoepitaxial Growth on Substrates with Different Off-Cut Directions

Homoepitaxial growth on 4° off-axis substrates with different off-cut directions, i.e. [11-20] and [1-100], was investigated using a commercial CVD reactor. The characteristics of the growth process on substrates with different off-cut directions were determined with respect to applicable C/Si ratio, growth rate and n- and p-type doping range. Stable step flow growth was achieved over a broad range of C/Si ratio at growth rates ~ 15 µm/h in both cases. The n-type doping level of epilayers can be controlled at least in the range from 5  1014 cm-3 to 3  1017 cm-3 on both types of substrates. Highly p-type epilayers with p = 2  1019 cm-3 can also be grown on [1-100] off-cut substrates. Hence, the growth process for standard substrates was successfully transferred to [1-100] off-cut substrates resulting in epilayers with similar doping levels. The dislocation content of the grown epilayers was investigated by means of defect selective etching (DSE) in molten KOH. For both off-cut directions of the substrates, similar densities of threading edge dislocations (TED), threading screw dislocations (TSD) and basal plane dislocations (BPD) were found in the epilayers. Epilayers with very low BPD density can be grown on both kinds of substrates. The remaining BPDs in epilayers are inclined along the off-cut direction of the substrate. The surface morphology and roughness was investigated by atomic force microscopy (AFM). The epilayers grown on [1-100] off-cut substrates are smoother than those on standard substrates.

Comparison between measurement techniques used for determination of the micropipe density in SiC substrates

Micropipe density (MPD) is a crucial parameter for silicon carbide (SiC) substrates that determines the quality, stability and yield of the semiconductor devices built on these substrates. The importance of MPD is underscored by the fact that all existing specifications for 6H- and 4H-SiC substrates set upper limits for it. Several methods for measuring the MPD are known, however, their reliability and applicability to various types of substrates (e.g. semiinsulating, conducting, etc.) has not been systematically studied. The subject of this paper is a comparative study of various techniques used for the MPD measurement accompanied by statistical analysis of the results. The study was initiated by several organizations working in the immediate field of silicon carbide or in closely related fields and included SiC substrate manufacturers, substrate consumers, equipment manufacturers and universities. The study represented a round robin experiment in which MPD was measured on thirty SiC wafers of various pedigrees. The values of MPD have been determined using both destructive and non-destructive techniques. The repeatability of each technique is analyzed and compared with that of other techniques.