Arno Kunzmann

Reuse Techniques for VLSI Design

From the Publisher: nReuse Techniques for VLSI Design is a reflection on the current state of the art in design reuse for microelectronic systems. To that end, it is the first book to gamer the input of leading experts from both research and application areas. These experts document herein not only their more mature approaches, but also their latest research results. nThe background and support from international organisations that enforce System-on-a-Chip (SoC) design by reuse- oriented methodologies are presented. This overview is followed by a number of technical presentations covering different requirements of the reuse domain. These are presented from different points of view, i.e., IP provider, IP user, designer, isolated reuse, intra-company or inter-company reuse. More general systems or case studies, e.g., metrics, are followed by comprehensive reuse systems, e.g., reuse management systems partly including business models. nMixed- signal and analog reuse approaches are also presented. In parallel to the digital domain, this area covers research in reuse database design. Design verification and legal aspects are two important topics that are closely related to the realization of design reuse. These hot topics are covered by presentations that finalize the survey of outstanding research, development and application of design reuse for SoC design. Reuse Techniques for VLSI Design is an invaluable reference for researchers and engineers involved in VLSI/ASIC design.

FPL Based Self-Test with Deterministic Test Patterns

This paper describes a new approach to synthesize a costefficient self-test hardware for a given set of deterministic test patterns. To minimize the test hardware effort, instead of all the patterns only a very small subset has to be selected such that an easy generation of all necessary test patterns is ensured. This procedure drastically decreases the storage requirements (over 80%) and therefore reduces distinctly the selftest hardware effort. The realization of an external self-test by a specific test chip was done with XILINX FPGAs, since field-programmable gatearrays are best-suited for applications with a low production volume. Experimental results on all the ISCAS benchmark circuits underline the efficiency of our approach.

Efficient random testing with global weights

This paper describes a new and highly efficient approach for weighted random pattern generation. In contrast to the state-of-the-art approaches, where input specific weights are computed, the proposed method is based on the computation of global weights. This set of a very few weights (e.g., 4 or 8) is pattern oriented and therefore, with each weight the generation of the related random patterns is uniquely specified. Starting with a deterministic test pattern set and the inherent pattern specific weights, columns or rows can be inverted such that the initial weights are maximized in order to minimize the number of random patterns. Our experiments with the prototype system POWER-TEST (Pattern Oriented WEighted Random TESTing) show that very high fault coverage can be achieved with low computation and implementation effort at low self-test hardware costs.

Generic design flows for project management in a framework environment

Due to the increasing complexity of CAD systems, project managers, engineers and designers have to be supported in handling an increasing number and variety of highly specialized tools. Recent research activities follow the goal, to integrate these tools in a unified framework, which enables concurrent engineering based on a controlled execution of design activities within a common environment. Today, framework services are typically restricted to design data management and integration facilities. This paper addresses the often neglected, but very important problem of design flow management with special emphasis on project management strategies. In contrast to other approaches a generic procedure is proposed which is driven by the inherent interdependencies between project specification, design team and tools. This approach provides a flexible, adaptive and transparent design flow management system.<<ETX>>

Resource-Oriented Load Distribution in a Framework Environment

In this paper the framework-based load distribution system FLODIS is presented. In order to reduce the overall design time, FLODIS provides a user-transparent distribution of design activities over a heterogeneous network of workstations. The distribution algorithm is mainly controlled by estimations about the required activity-specific resources that can be derived by user-defined data, recorded execution profiles and methodology information of the framework. Experimental data with several design flows and different design activities show that by the proposed distribution system the overall execution time can be distinctly reduced. Compared with conventional distribution systems an average reduction up to over 60% can be observed.

Basic Requirements for an Efficient Inter-Framework-Communication

For the design of complex electronic CAD systems, several frameworks have been proposed and implemented offering a different set of basic services, and therefore, supporting specific and dedicated design activities. In this paper the results of a case-study are summarized where two almost complementary frameworks have been coupled in order combine their advantages: (1) the JESSI-COMMON-Framework with special emphasis on design management, and (2) FMCAD (representing a widespread design environment of the electronic CAD domain) that is tuned on close tool integration and efficient data handling. As a result of this case-study the basic requirements for an efficient inter-framework-communication are described to indicate some trends for future framework developments.

Gate-delay fault test with conventional scan-design

In this paper a new algorithm for automatic test pattern generation for finding gate-delay faults will be presented. In contrast to the state-of-the-art approaches the necessary test pattern sequences are generated using the logic function of the circuit to be tested. This enables the usage of both conventional scan flipflops and boundary scan cells, instead of enlarged area-consuming scannable flipflops. Additionally, the test application time can be distinctly reduced since only one test pattern of each test pair has to be loaded into the scan register. Experimental results of the ISCAS-89 benchmark circuits illustrate the efficiency of this new approach.<<ETX>>

Self-test of sequential circuits with deterministic test pattern sequences

This article describes a new approach for synthesizing a cost-efficient self-test hardware for a given set of deterministic test pattern sequences. To minimize the test hardware effort instead of all the test sequences, only a very small subset will be selected such that a simple generation of all necessary test sequences will be ensured. This procedure drastically decreases the storage requirements (about 80%) and therefore distinctly reduces the necessary test hardware overhead. Experimental results on the ISCAS-S-benchmarks emphasize the efficiency of our approach.

An alternative view on weighted random pattern testing

This paper describes a new and highly efficient approach for weighted random test pattern generation. In contrast to the state-of-the-art approaches, where input specific weights are computed, the proposed self-test method is tuned on the computation of global, pattern oriented weights: with each weight the generation of the related random test patterns is uniquely specified. The proposed self-test method is based on a partly specified deterministic test pattern set.

Enhanced functionality by coupling the JESSI-COMMON-Framework with an ECAD framework

Within the electronic CAD domain there exist several frameworks each with a different set of services, which results in the specific support of dedicated design activities. One of the most innovative framework systems is the JESSI-COMMON-Framework (JCF). In contrast to JCF, a widespread ECAD framework (called FMCAD) has nearly complementary goals: while JCF offers strong support for working with consistent data concurrently, the basic functionality of FMCAD heavily supports the designer. In order to combine the advantages of both frameworks, a new hybrid framework was developed by combining JCF and FMCAD. As described in the paper, this ultimate goal could not yet be reached, but the achieved results and experience with the existing prototype emphasize that this integration and encapsulation could be very helpful for future frameworks.<<ETX>>