Arno Luppold

Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems

To improve the execution time of a program, parts of its instructions can be allocated to a fast Scratchpad Memory (SPM) at compile time. This is a well-known technique which can be used to minimize the programs worst-case Execution Time (WCET). However, modern embedded systems often use cached main memories. An SPM allocation will inevitably lead to changes in the programs memory layout in main memory, resulting in either improved or degraded worst-case caching behavior. We tackle this issue by proposing a cache-aware SPM allocation algorithm based on integer-linear programming which accounts for changes in the worst-case cache miss behavior.

Multi-Criteria Compiler-Based Optimization of Hard Real-Time Systems

Real-Time Systems often come with additional requirements apart from being functionally correct and adhering to their timing constraints. Common additional optimization goals are meeting code size requirements or the reduction of energy consumption. We show how to extend modern compiler frameworks to allow for optimizations towards multiple design criteria.

Bus-Aware Static Instruction SPM Allocation for Multicore Hard Real-Time Systems

Over the past years, multicore systems emerged into the domain of hard real-time systems. These systems introduce common buses and shared memories which heavily influence the timing behavior. We show that existing WCET optimizations may lead to suboptimal results when applied to multicore setups. Additionally we provide both a genetic and a precise Integer Linear Programming (ILP)-based static instruction scratchpad memory allocation optimization which are capable of exploiting multicore properties, resulting in a WCET reduction of 26% in average compared with a bus-unaware optimization. Furthermore, we show that our ILP-based optimizations average runtime is distinctively lower in comparison to the genetic approach. Although limiting the number of tasks per core to one and partially exploiting private instruction SPMs, we cover the most crucial elements of a multicore setup: the interconnection and shared resources.

Practical Challenges of ILP-based SPM Allocation Optimizations

Scratchpad Memory (SPM) allocation is a well-known technique for compiler-based code optimizations. Integer-Linear Programming has been proven to be a powerful technique to determine which parts of a program should be moved to the SPM. Although the idea is quite straight-forward in theory, the technique features several challenges when being applied to modern embedded systems. In this paper, we aim to bring out the main issues and possible solutions which arise when trying to apply those optimizations to existing hardware platforms.

Schedulability-aware SPM Allocation for preemptive hard real-time systems with arbitrary activation patterns

In hard real-time multi-tasking systems each task has to meet its deadline under any circumstances. If one or several tasks violate their timing constraints, compiler optimizations can be used to optimize the Worst-Case Execution Time (WCET) of each task with a focus on the systems schedulability. Existing approaches are limited to single-tasking or strictly periodic multitasking systems. We propose a compiler optimization to perform a schedulability-aware static instruction Scratchpad Allocation for arbitrary activation patterns and deadlines. The approach is based on Integer-Linear Programming and is evaluated for the Infineon TriCore TC1796 microcontroller.

A new concept for system-level design of runtime reconfigurable real-time systems

This concept paper proposes a new system-level design methodology for runtime reconfigurable adaptive heterogeneous systems in a real-time environment. Today, among those approaches dealing with runtime reconfiguration and hardware/software co-design, compliance with hard real-time conditions is not guaranteed. Our approach will fill this gap. In contrast to other approaches, we apply methods of real-time analysis to embedded reconfigurable systems. An extended compiler and a runtime resource manager guarantee both synthesis and reconfiguration in a (hard) real-time environment. With this approach, the system can adapt to changes in requirements and operational environments during runtime.

Mitigating Data Cache Aging through Compiler-Driven Memory Allocation

Many embedded systems have to operate flawlessly over several years. One of the key issues which may cause computational errors over time are memory errors inflicted by aging effects. We propose a compiler-based optimization in order to mitigate such effects on data caches using SRAM memory cells.

Measuring and Modeling Energy Consumption of Embedded Systems for Optimizing Compilers

Estimating energy consumption already during development as precisely as possible is crucial for many embedded system designs. These energy estimates should be expressed such that they can be used by subsequent automated optimizations during the compilation phase in order to minimize the expected energy consumption. In this paper we present our current approach on measuring and modeling, and subsequently using the derived energy estimates. Our model is implemented within an optimizing compiler, allowing for future energy focused compiler optimizations.

Automated generation of time-predictable executables on multicore

In this paper, we are interested in the implementation of control-command applications, such as the flight control system of an aircraft for instance, on multi-core hardware. Due to certification and safety issues, time-predictability - in the sense that the timing behavior must be analysable and validable off-line - is a mandatory feature. We present a complete framework, from high-level system specification in synchronous languages, to implementation on a multi-core hardware platform, which enforces time-predictability at every step of the development process. The framework is based on automated code generation tools to speed-up the development process and to eliminate error-prone human-made translation steps.

Schedulability Aware WCET-Optimization of Periodic Preemptive Hard Real-Time Multitasking Systems

In hard real-time multitasking systems, applying WCET-oriented code optimizations to individual tasks may not lead to optimal results with regard to the systems schedulability. We propose an approach based on Integer-Linear Programming which is able to perform schedulability aware code optimizations for periodic task sets with fixed priorities. We evaluate our approach by using a static instruction SPM optimization for the Infineon TriCore microcontroller.