Arthur Nieuwoudt

Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnects. This paper discusses the modeling of nanotube bundle resistance for on-chip interconnect applications. Based on recent experimental results, the authors model the impact of nanotube diameter on contact and ohmic resistance, which has been largely ignored in previous bundle models. The results indicate that neglecting the diameter-dependent nature of ohmic and contact resistances can produce significant errors. Using the resistance model, it is shown that SWCNT bundles can provide up to one order of magnitude reduction in resistance when compared with traditional copper interconnects depending on bundle geometry and individual nanotube diameter. Furthermore, for local interconnect applications, an optimum nanotube diameter exists to minimize the resistance of the carbon nanotube bundle

Understanding the Impact of Inductance in Carbon Nanotube Bundles for VLSI Interconnect Using Scalable Modeling Techniques

In this paper, we develop accurate and scalable models for the magnetic inductance in bundles of single-walled carbon nanotubes, which have been proposed as a means to alleviate the increasingly critical resistance problems associated with traditional copper interconnect in very large scale integration (VLSI) applications. The models consider the density and statistical distribution of both metallic and semiconducting nanotubes within the bundle. We evaluate the speed, accuracy, and scalability of our magnetic inductance modeling techniques and previously proposed inductance models. The inductance model with the best performance evaluates the magnetic inductance of nanotube bundles with excellent accuracy when compared to modeling each nanotube individually and provides orders of magnitude improvement in CPU time as the bundle size increases. Leveraging the magnetic inductance modeling techniques, we determine the relative impact of magnetic and kinetic inductance. Based on our results, the relative value of magnetic and kinetic inductance on single-walled carbon nanotube (SWCNT) bundles is highly dependent on the bundle geometry and the per unit length kinetic inductance

Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper interconnect as technology scales into the nanoscale regime. In this article, we evaluate the performance and reliability of nanotube bundles for both local and global interconnect in future VLSI applications. To provide a holistic evaluation of SWCNT bundles for on-chip interconnect, we have developed an efficient equivalent circuit model that captures the statistical distribution of individual metallic and semiconducting nanotubes while accurately incorporating recent experimental and theoretical results on inductance, contact resistance, and ohmic resistance. Leveraging the circuit model, we examine the performance and reliability of nanotube bundles for both individual signal lines and system-level designs. SWCNT interconnect bundles can provide significant improvement in delay and maximum current density over traditional copper interconnect, depending on bundle geometry and process technology. However, for system-level designs, the statistical variation in the delay of SWCNT bundles may lead to reliability issues in future process technology. Consequently, if the SWCNT chirality can be effectively controlled and other manufacturing challenges are met, SWCNT bundles potentially are a viable alternative to standard copper interconnect as process technology scales.

On the Optimal Design, Performance, and Reliability of Future Carbon Nanotube-Based Interconnect Solutions

In this paper, we develop comprehensive modeling and design techniques for carbon nanotube (CNT)-based interconnects, which we utilize to examine the performance, reliability, and fabrication requirements for future nanotube-based interconnect solutions. We create a generalized model for CNT-based interconnect systems that achieves a high degree of accuracy compared to experimental CNT measurements. Leveraging the model, we develop the first closed-form formulation for the optimal nanotube diameter and bundle height for multi-walled CNT (MWCNT) and single-walled CNT (SWCNT) bundle interconnects for a general set of geometric and process parameters. The results indicate that the proposed design method decreases delay by 21% and 29% on average compared to nonoptimized MWCNT and SWCNT bundles. We also find that future CNT bundle fabrication processes must achieve a nanotube area coverage of at least 30% for optimized CNT bundles and 40% for nonoptimized CNT bundles to obtain competitive performance results compared to copper interconnects. In terms of reliability, we find that large diameter MWCNT bundles are significantly more susceptible to process variations than SWCNT bundles, which will have important implications for their utilization in future nanoscale integrated circuits.

Variability-Aware Multilevel Integrated Spiral Inductor Synthesis

To successfully design spiral inductors in increasingly complex and integrated mixed-signal systems, effective design automation techniques must be created. In this paper, the authors develop an automated synthesis methodology for integrated spiral inductors to efficiently generate Pareto-optimal designs based on application requirements. At its core, the synthesis approach employs a scalable multilevel single-objective optimization engine that integrates the flexibility of deterministic pattern search optimization with the rapid convergence of local nonlinear convex optimization. Multiobjective optimization techniques and surrogate functions are utilized to approximate Pareto surfaces in the design space to locate Pareto-optimal spiral inductor designs. Using the synthesis methodology, the authors also demonstrate how to reduce the impact of process variation and other sources of modeling error on spiral inductors. The results indicate that the multilevel single-objective optimization engine locates near-optimal spiral inductor geometries with significantly fewer function evaluations than current techniques, whereas the overall synthesis methodology efficiently optimizes inductor designs with an improvement of up to 51% in key design constraints while reducing the impact of process variation and modeling error

On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect

Bundles of single-walled carbon nanotubes (SWCNTs) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current-carrying capabilities. Given the manufacturing challenges associated with future nanotube-based interconnect solutions, determining the impact of process variations on this new technology relative to standard copper interconnect is vital for predicting the reliability of nanotube-based interconnect. In this paper, we investigate the impact of process variations on future interconnect solutions based on carbon nanotube bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall three-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by up to 63% in 22-nm process technology

Multi-level approach for integrated spiral inductor optimization

The efficient optimization of integrated spiral inductors remains a fundamental barrier to the realization of effective analog and mixed-signal design automation. In this paper, we develop a scalable multi-level optimization methodology for spiral inductors that integrates the flexibility of constrained global optimization using mesh-adaptive direct search (MADS) algorithms with the rapid convergence of local nonlinear convex optimization techniques. Experimental results indicate that our methodology locates optimal spiral inductor geometries with significantly fewer function evaluations than current techniques.

Predicting the Performance of Low-Loss On-Chip Inductors Realized Using Carbon Nanotube Bundles

Within the analog realm, integrated inductors continue to limit the performance of mixed-signal systems. To improve the performance of integrated inductors for future mixed-signal systems, alternative technologies must be investigated. In this paper, we propose low-loss on-chip inductors leveraging single-walled carbon nanotube (SWCNT) bundles, which have the potential to provide conductors with significantly lower resistivity than traditional copper technology. We develop a model for high-frequency current redistribution in SWCNT bundles, which we find can have a large effect on the resistance and quality factor of nanotube-based inductors. Leveraging a compact RLC circuit model, we examine the potential quality factor improvement provided by nanotube-based inductors over copper-based inductors for mixed-signal circuit applications. The results indicate that the optimized SWCNT bundle-based inductors can potentially provide a significant increase in quality factor. To demonstrate the performance advantages of optimized nanotube-based inductors, we find that their increased quality factors can lead to a noise figure and power consumption improvement in low-noise amplifiers, which are critical radio frequency circuits in integrated wireless receivers. If the integrated circuit fabrication challenges associated with high-density nanotube-based wires can be overcome, nanotube-based inductors could enable future mixed-signal and wireless systems with greater performance.

Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations

In this paper, the authors develop several design techniques for reducing the impact of manufacturing variations on integrated wideband low noise amplifiers (LNA). Utilizing an efficient modeling and automated design methodology, the authors investigate the sensitivity of LNA performance metrics to process variations and determine that the input impedance matching is particularly sensitive to perturbations in component values. Based on the sensitivity analysis, the authors leverage several design techniques to increase the reliability of LNA designs. To mitigate the impact of process variations on the input impedance matching, the authors add additional circuit elements and tunable capacitors to dynamically compensate for manufacturing variations after fabrication. The results indicate that the proposed design techniques can increase manufacturing yield by up to one order of magnitude for input impedance matching with only a 14% increase in noise figure

Assessing carbon nanotube bundle interconnect for future FPGA architectures

Field programmable gate arrays (FPGAs) are important hardware platforms in various applications due to increasing design complexity and mask costs. However, as CMOS process technology continues to scale, standard copper interconnect becomes a major bottleneck for FPGA performance. This paper proposed utilizing bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric and compare their performance to standard copper interconnect in future process technologies. To leverage the performance advantages of nanotube-based interconnect, several important aspects of the FPGA routing architecture were explored including the segmentation distribution and the internal population of the wires. The results demonstrate that FPGAs utilizing SWCNT bundle interconnect can achieve a 19% improvement in average area delay product over the best performing architecture for standard copper interconnect in 22 nm process technology