Tamer Ragheb

Theory and Implementation of an Analog-to-Information Converter using Random Demodulation

The new theory of compressive sensing enables direct analog-to-information conversion of compressible signals at sub-Nyquist acquisition rates. The authors develop new theory, algorithms, performance bounds, and a prototype implementation for an analog-to-information converter based on random demodulation. The architecture is particularly apropos for wideband signals that are sparse in the time-frequency plane. End-to-end simulations of a complete transistor-level implementation prove the concept under the effect of circuit nonidealities.

Practical Issues in Implementing Analog-to-Information Converters

The stability and programmability of digital signal processing systems has motivated engineers to move the analog-to-digital conversion (ADC) process closer and closer to the front end of many signal processing systems in order to perform as much processing as possible in the digital domain. Unfortunately, many important applications, including radar and communication systems, involve wideband signals that seriously stress modern ADCs; sampling these signals above the Nyquist rate is in some cases challenging and in others impossible. While wideband signals by definition have a large bandwidth, often the amount of information they carry per second is much lower; that is, they are compressible in some sense. The first contribution of this paper is a new framework for wideband signal acquisition purpose-built for compressible signals that enables sub-Nyquist data acquisition via an analog-to-information converter (AIC). The framework is based on the recently developed theory of compressive sensing in which a small number of non-adaptive, randomized measurements are sufficient to reconstruct compressible signals. The second contribution of this paper is an AIC implementation design and study of the tradeoffs and non-idealities introduced by real hardware. The goal is to identify and optimize the parameters that dominate the overall system performance

A prototype hardware for random demodulation based compressive analog-to-digital conversion

In this paper, we utilize recent advances in compressive sensing theory to enable signal acquisition beyond Nyquist sampling constraints. We successfully recover signals sampled at sub-Nyquist sampling rates by exploiting additional structure other than bandlimitedness. We present a working prototype of compressive analog-to-digital converter (CADC) based on a random demodulation architecture. The architecture is particularly suitable for wideband signals that are sparse in the time-frequency plane. CADC has the advantage of enhancing the performance of communication and multimedia systems by increasing the transmission rate for the same bandwidth. We report successful reconstruction of AM modulated signals at sampling rates down to 1/8 of the Nyquist-rate, which represents an up to 87.5% savings in the bandwidth and the storage memory.

On the feasibility of hardware implementation of sub-Nyquist random-sampling based analog-to-information conversion

In this paper, we successfully demonstrate the feasibility of hardware implementation of a sub-Nyquist random- sampling based analog to information converter (RS-AIC). The RS-AIC is based on the theory of information recovery from random samples using an efficient information recovery algorithm to compute the spectrogram of the signal. Our RS-AIC enables sub-Nyquist acquisition and processing of wideband signals that are sparse in a local Fourier representation. Results from our RS-AIC hardware implementation demonstrate successful reconstruction of signals that are sampled at half the Nyquist-rate while maintaining up to a 51 dB signal-to-noise ratio (SNR), which is equivalent to an 8.5 bit resolution analog to digital converter.

Thermally robust clocking schemes for 3D integrated circuits

3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers. However, dissipating the heat generated in the 3D chips possesses a major challenge to the success of the technology and is the subject of active current research. Since the generated heat degrades the performance of the chip, thermally insensitive/adaptive circuit design techniques are required for better overall system performance. In this paper, we propose a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. We investigate the relative merits and demerits of two alternative clock tree topologies in this work. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by 61.65% on the average, leading to much improved clock synchronization and design performance in the 3D realm.

A fault-aware dynamic routing algorithm for on-chip networks

Given the spatial and temporal randomness of soft and permanent errors in the state-of-the-art system-on-chips (SoCs), dynamic routing algorithms that can adapt themselves accordingly are highly required for network-on-chip (NoC) applications. In this paper, we present a new dynamic routing algorithm for NoC applications that has the ability to locate and deal with both static and dynamic permanent failures and distinguish them from soft errors. In addition, our presented algorithm has the advantage of distributing the load over the whole network by considering the stress factors. Simulation results demonstrate the advantage of our routing algorithm in terms of functionality, latency, and energy consumption compared to directed flooding based fault tolerant routing algorithms in the presence of both soft errors and permanent faults. Our algorithm can achieves 1.95 times less latency and consumes 3.15 times less energy consumption on average.

Increasing Manufacturing Yield for Wideband RF CMOS LNAs in the Presence of Process Variations

In this paper, the authors develop several design techniques for reducing the impact of manufacturing variations on integrated wideband low noise amplifiers (LNA). Utilizing an efficient modeling and automated design methodology, the authors investigate the sensitivity of LNA performance metrics to process variations and determine that the input impedance matching is particularly sensitive to perturbations in component values. Based on the sensitivity analysis, the authors leverage several design techniques to increase the reliability of LNA designs. To mitigate the impact of process variations on the input impedance matching, the authors add additional circuit elements and tunable capacitors to dynamically compensate for manufacturing variations after fabrication. The results indicate that the proposed design techniques can increase manufacturing yield by up to one order of magnitude for input impedance matching with only a 14% increase in noise figure

Numerical Design Optimization Methodology for Wideband and Multi-Band Inductively Degenerated Cascode CMOS Low Noise Amplifiers

In this paper, we develop a systematic design optimization methodology for inductively degenerated cascode CMOS low noise amplifiers (LNA) in fully integrated wideband and multi-band wireless systems. Leveraging an accurate analytical circuit model, we combine global and local numerical optimization techniques in a hierarchical manner to simultaneously determine the fixed and switchable passive component and device parameters in the LNA circuit necessary to meet user-specified performance requirements. To demonstrate the effectiveness of proposed design optimization methodology, we utilize the method to create 3 wideband and 3 multi-band LNA designs that meet a wide-range of impedance matching, noise figure, gain, power dissipation, and linearity requirements. The proposed method provides circuit designers with a fast and effective means for the rapid prototyping and design space exploration of wideband and multi-band inductively degenerated cascode CMOS LNAs.

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

A network-on-chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, the authors quantify the fault tolerance offered by an NoC against process variations. Specifically, the authors develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, the authors study the impact of link failure on the number of cycles required to establish communications in NoC applications

Hierarchical Optimization Methodology for Wideband Low Noise Amplifiers

In this paper, we present a systematic synthesis methodology for fully integrated wideband low noise amplifiers that simultaneously optimizes impedance matching, noise figure, and other performance parameters. Leveraging an accurate analytical model, we hierarchically couple global optimization techniques with local convex optimization methods to efficiently locate optimal wideband LNA circuits. The results indicate that the methodology yields significant improvement in key LNA design constraints over existing methodologies while achieving up to one order of magnitude speedup in computational performance.