Rajiv K. Singh

Improved Transfer of Graphene for Gated Schottky-Junction, Vertical, Organic, Field-Effect Transistors

An improved process for graphene transfer was used to demonstrate high performance graphene enabled vertical organic field effect transistors (G-VFETs). The process reduces disorder and eliminates the polymeric residue that typically plagues transferred films. The method also allows for purposely creating pores in the graphene of a controlled areal density. Transconductance observed in G-VFETs fabricated with a continuous (pore-free) graphene source electrode is attributed to modulation of the contact barrier height between the graphene and organic semiconductor due to a gate field induced Fermi level shift in the low density of electronic-states graphene electrode. Pores introduced in the graphene source electrode are shown to boost the G-VFET performance, which scales with the areal pore density taking advantage of both barrier height lowering and tunnel barrier thinning. Devices with areal pore densities of 20% exhibit on/off ratios and output current densities exceeding 10(6) and 200 mA/cm(2), respectively, at drain voltages below 5 V.

Corrugated Sapphire Substrates for Organic Light-Emitting Diode Light Extraction

In an organic light-emitting diode (OLED), only about 20-30% of the generated light can be extracted because of the light lost to the thin film guided modes and surface plasmon. Using corrugated high-index-refractive substrates, the thin film guided modes can be effectively out-coupled from the device because of the high index substrate and the loss to the surface plamon is suppressed due to the corrugated structure. With an additional macro lens attached to the substrate to extract the substrate mode, we finally demonstrated a green phosphorescent OLED with an extremely high external quantum efficiency of 63%.

Method for Quantifying the Degree of Agglomeration in Highly Stable Chemical Mechanical Polishing Slurries

In chemical mechanical polishing (CMP) systems, slurry stability is qualitatively assessed through interparticle force or zeta potential measurements. However, these types of measurements do not fully describe agglomeration phenomena in CMP slurries. Therefore, we developed an experimental/theoretical approach for quantifying the degree of agglomeration in CMP slurries. This method involves subjecting the slurry to high-shear forces and measuring particle agglomeration characteristics in their tail distribution. By modeling changes in tail distribution using Smoluchowskis slow aggregation theory, the agglomeration index can be used to quantify the degree of agglomeration caused by external shear stress and internal slurry chemistry.

Strain induced changes in gate leakage current and dielectric constant of nitrided Hf-silicate metal oxide semiconductor capacitors

Uniaxial-mechanical-stress altered gate leakage current and dielectric constant of silicon metal-oxide-semiconductor (MOS) devices with nitrided Hf-silicate (HfSiON) dielectric are measured as a function of uniaxial stress applied using four-point wafer bending along the [110] direction. The gate leakage current and dielectric constant are found to increase by ∼2% per 100MPa of tensile and compressive stresses. A decrease in hole trap activation energy in hafnium oxide-based dielectric is used to explain the mechanical stress altered gate leakage. It is proposed that the HfSiON dielectric constant increase results from band gap narrowing caused by strain induced N p band splitting.

An Evaluation of Ti-Based Metal Gate Electrodes on Hf-Silicate Dielectrics for Dual-Metal-Gate Applications

An evaluation of Ti-based gate metals (Ti, TiN, and TiB 2 ) on Hf-silicate gate dielectric prepared by atomic layer deposition has been reported. The effective metal work functions, calculated by taking an interface layer and interface charge into consideration, were 4.27, 4.56, and 5.08 eV for Ti, TiN, and TiB 2 , respectively. Regardless of gate electrodes, the conduction mechanism of the samples was fitted with the Poole-Frenkel model, which is related to oxygen vacancies in the film. A Ti gate electrode was found to be more favorable for n-channel metal oxide semiconductor (MOS) devices, and TiB 2 gate electrode can be used for p-channel MOS devices with Hf-silicate dielectrics.

Microlens Array Fabrication by Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) was used to shape hexagonally arranged 20 μm diam cone-shaped structures, prepared by wet etching of Coming 2496 glass, into microlenses. Edge rounding, which occurs during CMP due to a higher removal rate at the edges, was utilized for shaping of the microlenses. Microlenses with an H/D ratio of ∼ 1/10 and radius of curvature of 27.5 μm were obtained. CMP variables that affect the contact pressure and material removal rate are downpressure, linear velocity, slurry, and properties of the pad. These variables being external to substrate provide great flexibility and, hence, suitability of the process for a wide range of materials.

Micro-architecture embedding ultra-thin interlayer to bond diamond and silicon via direct fusion

The continuous demand on miniaturized electronic circuits bearing high power density illuminates the need to modify the silicon-on-insulator-based chip architecture. This is because of the low thermal conductivity of the few hundred nanometer-thick insulator present between the silicon substrate and active layers. The thick insulator is notorious for releasing the heat generated from the active layers during the operation of devices, leading to degradation in their performance and thus reducing their lifetime. To avoid the heat accumulation, we propose a method to fabricate the silicon-on-diamond (SOD) microstructure featured by an exceptionally thin silicon oxycarbide interlayer (∼3 nm). While exploiting the diamond as an insulator, we employ spark plasma sintering to render the silicon directly fused to the diamond. Notably, this process can manufacture the SOD microarchitecture via a simple/rapid way and incorporates the ultra-thin interlayer for minute thermal resistance. The method invented herein expects to minimize the thermal interfacial resistance of the devices and is thus deemed as a breakthrough appealing to the current chip industry.

Study of interface degradation of Hf-silicate gate dielectrics during thermal nitridation process

An evaluation of the effect of nitridation temperature on interface layer (IL) quality of Hf-silicate gate dielectric prepared by the atomic layer deposition method has been reported. An increase in IL density and IL roughness was observed by x-ray reflectivity as the nitridation temperature was increased. X-ray photoelectron spectroscopy showed preferential interface reaction at the dielectric-Si interface at higher temperatures. The progressive increase in IL roughness finally led to degradation of the breakdown voltage, a shift in flat band voltage (∼0.54V), and deterioration of electron channel mobility by ∼20% in samples nitrided at 850°C.

High efficiency nitrogen incorporation technique using ultraviolet assisted low temperature process for hafnia gate dielectric

An evaluation of a low temperature process (∼350°C) for nitrogen incorporation in hafnia gate dielectric has been reported. This method is based on postdeposition nitridation under ultraviolet light illuminated NH3 ambience. X-ray photoelectron spectroscopy confirmed the amount of nitrogen incorporated by this process was comparable to that of high temperature (∼650°C) thermal nitridation (∼7%). Uniformity of nitrogen distribution in the film was analyzed by secondary ion mass spectroscopy. A capacitance density of ∼3.96μF∕cm2 with 9.4A equivalent oxide thickness and 10A thick interface layer were obtained by ultraviolet assisted nitridation process.