Arvind Sundararajan

SysGen for DSP

DSP systems generally transform a stream of sampled inputs to a stream of sampled outputs. The sampled inputs are usually the result of an analog to digital converter sampling the output of a sensor. Development of a DSP algorithm involves transforming these input samples using numerous mathematical operations like convolution or performing Fast Fourier Transform (FFT). The implementation of these algorithms requires many visualization aids like plotting the spectral density of the output signal or creating scatter plots of complex signals. Development of these systems and algorithms on an FPGA using traditional RTL techniques is very labor intensive due to the lack of libraries to create domain-specific stimulus generators and visualizers. Much of the time would be spent simply creating test benches that try to emulate the deployment environment (Fig. 8.1).