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Featured researches published by Asao Nishimura.


electronic components and technology conference | 1998

Chip scale packaging for memory devices

Yasuhiro Akiyama; Asao Nishimura; Ichiro Anjoh

A low cost, high reliability chip scale package has been developed for memory devices. The developed CSP can be applied to center pad type devices such as DRAM and to peripheral pad type devices such as SRAM and Flash. Reliability and high volume productivity are the main technological challenges that have to be overcome for chip scale packaging. This paper unveils Hitachis original CSP concept and shows how our CSP overcomes these challenges.


Materials Science Forum | 2007

Whisker Initiation Behavior from Electrodeposited Sn/Cu Coating on Cu Leadframe

Takahiko Kato; Haruo Akahoshi; Takeshi Terasaki; Tomio Iwasaki; Masato Nakamura; Tomoaki Hashimoto; Asao Nishimura

Tin/copper (Sn/Cu) coatings on Cu leadframes (CUFE), in which Fe atoms are doped as a minor element, showed whisker initiation at room temperature over a long period of 47 months. By means of the planar slice method and electron back scattering pattern (EBSP) measurement, the whisker roots were consistently found to be located at the intersections of grain boundaries in the coating. Whisker roots were also located above the peaks and ridge lines of intermetallic compound (IMC) Cu6Sn5, which was formed with a pyramid-shaped configuration between the Sn/Cu coating and Cu leadframe. Using finite element analysis (FEA), we calculated stress distribution in the coating. The results indicated that compressive stress normal to the grain boundary was induced with a gradient toward the surface in the coating. Therefore, the compressive stress gradient induced by the pyramid-shaped IMC is thought to be the root cause of whisker initiation in Sn/Cu coatings on Cu leadframes. When the Cu leadframe with a minor doped element of Cr atoms (CUCR) was used as the substrate with the same Sn/Cu coating, no whisker initiation was observed even after a longer storage time of 65 months. Through field-emission scanning transmission electron microscopy (FE-STEM) and field-emission transmission electron microscopy (FE-TEM) microstructural observations of vertical sections of each sample, the shape of the IMCs formed between the coating and the leadframe in the Sn/Cu-CUFE sample was found to be different from that in the Sn/Cu-CUCR sample. The difference in whisker initiation tendency can therefore be explained by the difference in compressive stress depending on the shape of the Cu-Sn IMCs, because stress distribution in the coating of the Sn/Cu-CUCR sample calculated using FEA revealed a smaller stress gradient than that in the Sn/Cu-CUFE sample.


electronic components and technology conference | 2008

Stress measurement by X-Ray diffraction method for electrodeposited SnCu coating on alloy 42 substrate

Takahiko Kato; Haruo Akahoshi; Masato Nakamura; Tomoaki Hashimoto; Asao Nishimura

A stress measurement method using SnCu coating on an Alloy 42 substrate sample, which indicated non-linear sin2 Psi diagram for the coating under ordinary X-ray diffraction conditions was investigated. Diffraction profile versus 2thetas diagrams for peak indexes of (312), (501), (213), (600), (323), (541), and (631) obtained using an iso inclination method and a fixed Psi method using CuKalpha radiation showed clear peaks for some Psi angles. However, in other cases, the diagrams showed flat forms (no peaks). It was found that removing the Psi data with the flat forms from the diffraction profile versus 2thetas diagram gave a linear sin2Psi diagram for each index. Indexes with higher 2thetas degrees had a smaller confidence limit. The (631) peak with the highest 2thetas degree, which had no flat forms in the diffraction profile versus the 2thetas diagram, even with seventeen Psi data points, indicated a linear sin2thetas diagram and a confidence limit of less than plusmn2 MPa.


Archive | 1992

Semiconductor integrated circuit device and manufacture thereof

Asao Nishimura; Syouji Syukuri; Gorou Kitsukawa; Toshio Miyamoto


Archive | 1999

Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes

Asao Nishimura; Syouji Syukuri; Gorou Kitsukawa; Toshio Miyamoto


Archive | 2002

Wafer level chip size package having rerouting layers

Toshio Miyamoto; Ichiro Anjo; Asao Nishimura; Mitsuaki Katagiri; Yuji Shirai; Yoshihide Yamaguchi


Archive | 2000

Semiconductor device provided with rewiring layer

Akihiro Yaguchi; Hideo Miura; Atsushi Kazama; Asao Nishimura


Archive | 2004

Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device

Masahiko Ogino; Takumi Ueno; Shuji Eguchi; Akira Nagai; Toshiya Satoh; Toshiaki Ishii; Hiroyoshi Kokaku; Tadanori Segawa; Nobutake Tsuyuno; Asao Nishimura; Ichiro Anjoh


Archive | 2002

Semiconductor device comprising stress relaxation layers and method for manufacturing the same

Akira Nagai; Takumi Ueno; Haruo Akahoshi; Syuji Eguchi; Masahiko Ogino; Toshiya Satoh; Asao Nishimura; Ichiro Anjoh


Archive | 2001

Method of manufacturing a ball grid array type semiconductor package

Chuichi Miyazaki; Yukiharu Akiyama; Masanori Shibamoto; Tomoaki Kudaishi; Ichiro Anjoh; Kunihiko Nishi; Asao Nishimura; Hideki Tanaka; Ryosuke Kimoto; Kunihiro Tsubosaki; Akio Hasebe

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