Ichiro Anjoh

Advanced IC packaging for the future applications

The performance of electronic equipment is improving rapidly. Portable electronic equipment requires smaller and thinner packaging systems for saving space and miniaturization. In addition, highly integrated, high-speed applications demand improved electrical performance to minimize noise effects. As a result of these considerations, the role of IC packaging has expanded from its traditional role of protecting the integrity and performance of an IC, to being a central factor in the development of electronic system concepts. In developing the optimum system, packaging technology must be a prime design consideration to ensure optimum performance, reliability, and cost. Soldering technology and Printed Wiring Board (PWB) routing density are two of the major technological issues facing miniaturized packaging systems today. Chip Scale Package (CSP), which is a new concept in packaging technology has been introduced. This is an ideal technology to enable the design and manufacture of the next generation of electronic equipment, while overcoming many of the technological issues facing system development.

Development of low-cost and highly reliable wafer process package

A wafer level chip-scale-package (WLCSP) is expected to reduce the manufacturing cost of CSPs, but reliability of a solder joint for a large chip size of about 100 mm/sup 2/ without underfill assembly is still in question. To meet this needs, we have developed a highly reliable and low-cost WLCSP named wafer process package phase 2 (WPP-2). The package includes a built-in stress-relaxation layer for reducing the strain of the solder bumps. To lower the manufacturing cost of the package, the stress-relaxation layer is formed by printing. The Youngs modulus and the thickness of the stress relaxation layer were optimized by finite element analysis. The package was assumed to have 10/spl times/10 mm chip and 54 Sn-Ag-Cu solder balls of 400-/spl mu/m diameter placed as a grid array with the minimum pitch of 0.8 mm, and be mounted on a FR-4 motherboard. It was found that a thickness of 75-/spl mu/m and a Youngs modulus of 1000 MPa are necessary for assuring no failure up to 1000 cycles under temperature cycling between -55 and 125/spl deg/C. Accordingly, a resin with a Youngs modulus of about 1200 MPa at -55/spl deg/C was developed for the stress relaxation layer. High reliability of the simulated WPP-2 structure was confirmed by simplified test samples made of the developed resin. Fully processed WPP-2 samples were fabricated on an 8-inch wafer. The lifetime of the solder joints mounted on the FR-4 motherboard was evaluated by the temperature cycling test. The contact resistance of none of 50 samples increased by more than 20% even after 1400 cycles, and their lifetime to 50% failure was more than 3000 cycles.

Chip scale packaging for memory devices

A low cost, high reliability chip scale package has been developed for memory devices. The developed CSP can be applied to center pad type devices such as DRAM and to peripheral pad type devices such as SRAM and Flash. Reliability and high volume productivity are the main technological challenges that have to be overcome for chip scale packaging. This paper unveils Hitachis original CSP concept and shows how our CSP overcomes these challenges.