Aseem Gupta

LEAF: A System Level Leakage-Aware Floorplanner for SoCs

Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level leakage aware floorplanner (LEAF) which optimizes floorplans for temperature-aware leakage power along with the traditional metrics of area and wire length. Our floorplanner takes a SoC netlist and the dynamic power profile of functional blocks to determine a placement while optimizing for temperature dependent leakage power, area, and wire length. To demonstrate the effectiveness of LEAF, we implemented our methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and evaluated the trade-off between leakage power and area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage aware floorplanning.

Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability

In this paper we propose thermal aware global routing of interconnects which reduces the probability of failure of chips due to interconnect failures. Temperature has a very serious effect on the mean time to failure (MTF) of interconnects because of electromigration. We present TAGORE, a thermal aware global router. TAGORE achieves a reduction in the probability of failure by routing more wires in the colder regions of the chip and less wires in the hotter regions of the chip. We observed that TAGORE reduced the number of wires in the hottest region of a chip by up to 19.95 % and by an average of 12.29 %. This resulted in a decrease in the failure rate by up to 292 failures per million hours of operation. We also perform an analytical examination of the reduction in the probability of interconnect failure and the failure rate. The analysis shows that there is a reduction in the probability of failure of a chip if fewer wires are routed in the hot regions. This approach to reliability improvement does not require any addition of redundant wires or vias.

RELOCATE: register file local access pattern redistribution mechanism for power and thermal management in out-of-order embedded processor

In order to reduce register files peak temperature in an embedded processor we propose RELOCATE: an architectural solution which redistributes the access pattern to physical registers through a novel register allocation mechanism. RELOCATE regionalizes the register file such that even though accesses within a region are uniformly distributed, the activity levels are spread over the entire register file in a deterministic pattern. It partitions the register file and uses a micro-architectural mechanism to concentrate the accesses to a single or a subset of such partitions through a novel register allocation mechanism. The goal is to keep some partitions unused (idle) and cooling down. The temperature of idle partitions is further reduced by power gating them into destructive sleep mode to reduce their leakage power. The redistribution mechanism changes the active region periodically to modulate the activity within the register file and prevent the active region from heating up excessively. Our approach resulted in an average reduction of 8.3°C in the register files peak temperature for standard benchmarks.

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs

In this paper the authors demonstrate the impact of the floorplan on the temperature-dependent leakage power of a system on chip (SoC). We propose a novel system level temperature aware and floorplan aware leakage power estimator, STEFAL, which considers both the floorplan of the SoC and the cycle-by-cycle dynamic power behavior while estimating the leakage power. The authors implemented our estimation methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and observed up to a 190% difference in the leakage power between various floorplans, clearly showing the importance of considering the floorplans and the temperature profile during leakage power estimation

Floorplan driven leakage power aware IP-based SoC design space exploration

Multi-million gate system-on-chip (SoC) designs increasingly rely on intellectual property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP blocks has risen thus leading to possible thermal runaway. In IP-based design there has been a disconnect between system level design and physical level steps such as floorplanning which can lead to failures in manufactured chips. This necessitates coupling between system level and physical level design steps. The leakage power of an IP-block increases with its temperature which is dependent on the SoCs floorplan due to thermal diffusion. We have observed that different floorplans of the same SoC can have up to 3X difference in leakage power. Hence the system designer needs to be aware of this design space between floorplans and leakage power. We propose a leakage aware exploration (LAX) framework which enables the system designer to create this design space early in the design cycle and provides an opportunity to make changes in the system design. We show the size of the design space generated by applying LAX on ten industrial SoC designs from Freescale Semiconductor Inc. and observe that the leakage power can vary by as much as 190% for 65% difference in the inactive area.

TRAM: a tool for temperature and reliability aware memory design

Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total systems power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5times while attaining an identical predefined limit on errors.

Performance analysis of embedded systems in the virtual component co-design environment

Due to the increasing complexity of embedded systems in terms of functionality and architectural resources available to meet performance and cost criteria, there is an added responsibility on the designer to make the right choices. These choices can differ in terms of different hardware/software partitions, different types of architectural components, different communication architectures etc. and each choice meets certain performance metrics up to certain level. In this paper, we are exploring the design space to analyze different choices of design implementations by quantitative estimation of performance during simulation. Multicriteria decision making (MCDM) methods are used to rank our choices. To demonstrate the validity of the above exploration technique, a codesign tool from Cadence - virtual component codesign (VCC) is used. It gives us the flexibility to create the experimental frame setup and probes to measure the performance metrics during simulations. The tradeoffs between performance metrics are performed by MCDM. A safety critical example is chosen to demonstrate our approach.

Embedded system engineering using C/C++ based design methodologies

This paper analyzes and compares the effectiveness of various system level design methodologies in assessing performance of embedded computing systems from the earliest stages of the design flow. The different methodologies are illustrated and evaluated by applying them to the design of an aircraft pressurization system (APS). The APS is mapped on a heterogeneous hardware/software platform consisting of two ASICs and a microcontroller. The results demonstrate the high impact of computer aided design (CAD) tools on design time and quality.

On chip Communication-Architecture Based Thermal Management for SoCs

In current Systems-on-Chip (SoC) designs, managing peak temperature is critical to ensure operation without failure. Our novel Communication Architecture Based Thermal Management (CBTM) scheme manages thermal behavior of components by delaying the execution of chosen IP-blocks or components by regulating the flow of data over the on-chip communication bus. This temperature aware traffic flow over the bus is achieved by dynamically changing the communication priority table in response to thermal readings from sensors. With CBTM, the temperatures of individual components can be controlled selectively. In this paper we demonstrate the effectiveness of CBTM on four industrial size SoC designs and also evaluate its performance impact. We observe that CBTM maintained thermal thresholds and reduced the peak temperature of an SoC by as much as 29°C.

Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units

Leakage currents in on-chip SRAMs: caches, branch predictor, register files and TLBs, are major contributors to the energy dissipated by processors in deep sub-micron technologies. High leakage also increases chip temperature and some SRAM-based structures become thermal hotspots. Previous work has addressed major sources of SRAM leakage in memory cells and bit-lines, making remaining SRAM components, in particular large drivers, the primary source of leakage. This paper proposes an approach to reduce this source of leakage in all major SRAM-based units of the processor, controlling them in a uniform way, yet treating each unit individually based on its behavior and memory organization. The new approach uses multiple bias voltages in sleep transistors allowing a trade-off between leakage reduction and wakeup delay in multi-stage peripheral drivers. Four low-power modes are defined, from basic to ultra low power, and SRAMs dynamically transition between these modes to minimize leakage without sacrificing performance. A novel control mechanism monitors and predicts future processor behavior for mode control. The leakage reduction in individual units is evaluated and shown to vary from 25% for IL1 to 75% for L2 caches. Resulting temperature reduction, including the effect of positive feedback between temperature and leakage power, is evaluated. A significant temperature reduction is achieved in each unit. It is also shown to reduce hot spots in the instruction TLB and branch predictor.