Anand Seshadri

A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process

A low-voltage (1.3 V) 64-Mb ferroelectric random access memory (FRAM) using a one-transistor one-capacitor (1T1C) cell has been fabricated using a state-of-the-art 130-nm transistor and a five-level Cu/flouro-silicate glass (FSG) interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate-oxide low-voltage logic process. Novel overwrite sense amplifier and programmable ferroelectric reference generation schemes are employed for fast reliable read-write cycle operation. Address access time for the memory is less than 30 ns while consuming less than 0.8 mW/MHz at 1.37 V. An embedded FRAM (eFRAM) density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks

In state-of-the-art technologies, the currents in all n-channel field-effect transistor device terminals can be severely degraded when a soft or hard dielectric breakdown event occurs from gate-to-drain. The equivalent circuits that are commonly used for modeling gate-to-drain breakdown do not adequately capture all of the salient features of post breakdown device characteristics and can yield results that are overly optimistic. We present an equivalent circuit comprehending both soft and hard breakdown that can be used to accurately model gate, drain, and source currents following a breakdown event from gate-to-drain.

A 64 Mbit embedded FeRAM utilizing a 130 nm, 5LM Cu/FSG logic process

A low-voltage (1.3V), 64 Mbit Ferroelectric Random Access Memory using a 1-transistor, 1-capacitor (1T1C) cell is demonstrated. This is the largest FRAM memory demonstrated to date. The memory is constructed using a state-of-the-art 130 nm transistor and a five-level Cu/FSG interconnect process. Only two additional masks are required for integration of the ferroelectric module into a single-gate oxide, low-voltage logic process. Address access time for the memory is less than 30 ns while consuming 0.57 mW/MHz at 1.37 V. An eFRAM density of 1.13 Mb/mm/sup 2/ is achieved with a cell size of 0.54 /spl mu/m/sup 2/ and capacitor size of 0.25 /spl mu/m/sup 2/.

An embedded DRAM module using a dual sense amplifier architecture in a logic process

A dual sense amplifier array architecture (DSSA) amenable to a logic-process-compatible 1T DRAM eliminates the penalty that can be imposed by any two-bank-architecture-based DRAM. A 32k/spl times/16 eDRAM test chip is used to verify the architecture. The chip is implemented in a 0.5 /spl mu/m single-poly, triple-metal CMOS process. The DRAM array cell capacitance and bitline parasitic capacitance are 23 fF and 550 fF, respectively. The DRAM cell is 33 /spl mu/m/sup 2/ (7.38/spl times/4.5 /spl mu/m/sup 2/).

The dynamic stability of a 10T SRAM compared to 6T SRAMs at the 32nm node using an accelerated Monte Carlo technique

An accelerated Monte Carlo technique is proposed to analyze the dynamic stability margin of SRAM cells. This technique greatly improves accuracy of the desired failure probabilities by, not approximating or making assumptions of fail tail distributions, enhancing fail rate with acceleration, while reducing computations by several orders of magnitude. An application comparing three 6 T SRAM cells and a novel 10 T SRAM cell at the 32 nm node is discussed.