Ashis Kumar Mal

Design of tunable folded cascode differential amplifier using PDM

Operational Amplifiers (op-amps) are one of the most commonly used blocks in analog and mixed signal VLSI design. Designers often spend considerable time in designing op-amps analytically, and then realize that the simulated circuits do not match with analytical expectations. This is primarily due to modeling of short channel MOS devices using long channel equations. Finally an adhoc mechanism is adopted to realize the op-amp with the help of a simulator. Proposed Potential Distribution Method (PDM) is a method where the design methodology is based on actual behavior of the devices and it is free from any analytical expression. This paper demonstrates the design approach for realizing a fully differential folded cascode op-amp using PDM, which is based on simulator results obtained with predefined bias conditions. The dependency of various performance parameters, like slew rate (SR), unity gain bandwidth (UGB), phase margin (PM), etc. on potentials and current distribution at different nodes is presented. It is found that using these dependencies, the target specifications for an op-amp can be achieved with shorter design time. Also, fine tuning the performance metric can be achieved using PDM. Finally, a fully differential folded cascode op-amp is thus designed and the simulation results are presented.

A low voltage high output impedance bulk driven regulated cascode current mirror

This work proposes the design of a new low voltage high output impedance CMOS current mirror that offers enhanced output voltage compliance using bulk-driven technique. The input/output characteristics of the proposed current mirror are discussed. Designed circuit is simulated in a proprietary 180 nm CMOS process, using Cadence Spectre and BSIM3v3 models. Simulated results with 0.8 V power supply and 50 uA input current reveal that the proposed implementation requires a minimum input and output voltages of 0.4 V and 0.39 V respectively. It yields an increase of the output impedance compared with that of existing bulk driven current mirrors, thus offering a potential solution to mitigate the effect of ultra-deep submicron CMOS transistors used in sub 1-V current mirrors and current sources. Compared to high output impedance gate driven regulated cascode current mirror (GDRCCM), low voltage high output impedance body driven regulated cascode current mirror (BDRCCM) supports higher output voltage swing. Thus, the proposed design finds wide acceptability in low voltage and low power CMOS analog integrated circuits.

A digitally programmable folded cascode OTA with variable load applications

Folded Cascode OTA is widely used in analog and mixed signal domain. It gains special importance in switched capacitor circuits where folded cascode architecture is the default choice for op-amps. In this work, a digitally programmable single ended folded cascode operational transconductance amplifier (OTA) is presented. Observations show that the OTA can be made digitally programmable over a wide range of unity gain frequency with compromise on phase margin. It is also shown that adding additional load branches in parallel allows wide tuning of the DC gain and phase margin. The programmable OTA is thus designed and the pre and post layout simulation results are presented.

Sealed-bid auction: a cryptographic solution to bid-rigging attack in the collusive environment

Sealed-Bid auction is an efficient and rational way to establish the price and trading goods in the open market. However sealed-bid auctions are subject to bid-rigging attack. Receipt-free mechanisms are proposed to prevent bid-rigging. So far, all the proposed receipt-free mechanisms are based on strict assumptions: i The channel between bidders and the auction authorities like auctioneer, sealer, registering authority etc. must be untappable, 2 the authorities are assumed to be honest not colluded, hence ensure privacy and anonymity of bids. Moreover, the existing receipt-free mechanisms are bandwidth intensive estimated difference between the minimum and maximum bidding price. In this paper, we present a receipt-free sealed-bid auction mechanism which can withstand public channel and colluded authorities. The proposed mechanism can work even under the situation where all the authorities except one are colluded. Unlike the existing mechanisms, the computational complexity of the proposed mechanism is independent of the bandwidth and only depends on the number of valid bids. The auction mechanism requires Omlogm computational steps to resolve the winner, where m is the number of valid bids in the system. Copyright

Practical Receipt-Free Sealed-Bid Auction in the Coercive Environment

Sealed-Bid auction is an efficient and rational method to establish the price in open market. However sealed-bid auctions are subject to bid-rigging attack. Receipt-free mechanisms were proposed to prevent bid-rigging. The prior receipt-free mechanisms are based on two assumptions; firstly, existence of untappable channel between bidders and auction authorities. Secondly, mechanisms assume the authorities to be honest (not colluding). Moreover the bandwidth required to communicate the receipt-free bids is huge. This paper presents a sealed-bid auction mechanism to resist bid-rigging. The proposed method does not assume untappable channel nor consider the authorities to be necessarily honest. The proposed mechanism also manages the bandwidth efficiently, and improves the performance of the system.

Coercion Resistant MIX for Electronic Auction

Coercion in sealed-bid auction refers to the problem of bid-rigging, where the adversary (coercer) dictates the bidder (coerced bidder) to bid some low value and also feasible to determine whether the victim has complied with the demands. Therefore uncoerciveness is an essential property to achieve fair and competitive sealed-bid auction. Receipt-free mechanisms are developed to confine the property of uncoerciveness. The prior receipt-free schemes assume an impractical assumption of the availability of an untappable channel between bidders and the auction authorities. Our previous work proposed a sender-side deniable encryption scheme to relax the assumption of the untappable channel where the receiver side is not colluded. However, we examined that neither the untappable channel nor the deniable encryption can provide receipt-freeness in presence of colluded authorities unless the privacy of the bidders are not preserved. MIX (MIX-cascade) is a well known technique for anonymous communication. This paper presents a MIX scheme compatible with deniable encryption to facilitate the receipt-freeness mechanisms to be practical without the assumption of untappable channel and also in the presence of colluded authorities. The proposed MIX may replace the untappable channel without changing the existing receipt-free mechanisms.

Non Overlapping Clock (NOC) generator for low frequency switched capacitor circuits

Switched capacitor techniques are very popular for implementation of Mixed Signal blocks in CMOS VLSI. Non-Overlapping Clock (NOC) generator is one of the key blocks in the implementation of switched capacitor circuits. Standard NOC generator circuits available in the literature uses delay circuits realized using simple inverters connected in a chain. For moderate frequencies, the number of inverters required for a reasonable non-overlapping period is nominal; however, for low frequency applications such as bio-medical signal processing, the number could be quite large. This affects the area and power budget of the design. In this work it is proposed to use inverters in inverted form to realize significant delay with less number of transistors. Simulation results suggest that the proposed circuit will be area and power efficient as compared to the conventional NOC circuits.

A family of flexible offset-time based wavelength schedulers for OBS edge-nodes

A family of variable offset-time based wavelength scheduling schemes for OBS edge-nodes, is proposed which performs 4-20 times better than ordinary LAUC-VF schedulers in terms of byte loss rate (ByLR). The schedulers accept a minimum and a maximum limit of offset-time along with the length of the burst as input and then return the appropriate wavelength and the exact offset-time, to be used for the burst. The basic principle is to align the burst either at the beginning or at the end of an existing void so that no new void is created after scheduling the burst unless mandated by the offset-time limits.

Non Overlapping Clock generator for switched capacitor circuits in Bio-Medical applications

Switched capacitor circuits have become a popular method for implementing mixed signal blocks in standard CMOS technologies. Non-Overlapping Clock (NOC) generator is a key building block of switched capacitor circuits. Standard NOC circuits use simple inverters to realize delays. For high to moderate frequencies, the number of inverters required is nominal. But for low frequency applications like Bio-Medical Signal Processing, the number of inverters increase drastically affecting the area and power budget. In this work it is proposed to use an inverter in inverted form along with a simple inverter as an inverting circuit to realize significant delay with lesser number of transistors. Simulation results suggest that the proposed inverter is area and power efficient.

A Novel and Efficient Approach for RC Delay Evaluation of On-chip VLSI Interconnect under Current Mode Signaling Technique

Current-mode signaling significantly increases the bandwidth of on-chip interconnects compared to voltage mode signaling and reduces the overall propagation delay. A delay formula for current mode is necessary for estimation of delay and bandwidth for VLSI systems. In this paper, closed-form expression of delay model based on the effective lumped element resistance and capacitance approximation of distributed RC lines are presented. A new closed-form solution of delay under step input excitation is developed. The usefulness of this solution is that both resistive and capacitive load termination is accurately modeled for use in current mode signaling . Comparison of simulation results with other established models justifies the accuracy of our approach.