Rishi Todani

Design of tunable folded cascode differential amplifier using PDM

Operational Amplifiers (op-amps) are one of the most commonly used blocks in analog and mixed signal VLSI design. Designers often spend considerable time in designing op-amps analytically, and then realize that the simulated circuits do not match with analytical expectations. This is primarily due to modeling of short channel MOS devices using long channel equations. Finally an adhoc mechanism is adopted to realize the op-amp with the help of a simulator. Proposed Potential Distribution Method (PDM) is a method where the design methodology is based on actual behavior of the devices and it is free from any analytical expression. This paper demonstrates the design approach for realizing a fully differential folded cascode op-amp using PDM, which is based on simulator results obtained with predefined bias conditions. The dependency of various performance parameters, like slew rate (SR), unity gain bandwidth (UGB), phase margin (PM), etc. on potentials and current distribution at different nodes is presented. It is found that using these dependencies, the target specifications for an op-amp can be achieved with shorter design time. Also, fine tuning the performance metric can be achieved using PDM. Finally, a fully differential folded cascode op-amp is thus designed and the simulation results are presented.

A digitally programmable folded cascode OTA with variable load applications

Folded Cascode OTA is widely used in analog and mixed signal domain. It gains special importance in switched capacitor circuits where folded cascode architecture is the default choice for op-amps. In this work, a digitally programmable single ended folded cascode operational transconductance amplifier (OTA) is presented. Observations show that the OTA can be made digitally programmable over a wide range of unity gain frequency with compromise on phase margin. It is also shown that adding additional load branches in parallel allows wide tuning of the DC gain and phase margin. The programmable OTA is thus designed and the pre and post layout simulation results are presented.

Non Overlapping Clock (NOC) generator for low frequency switched capacitor circuits

Switched capacitor techniques are very popular for implementation of Mixed Signal blocks in CMOS VLSI. Non-Overlapping Clock (NOC) generator is one of the key blocks in the implementation of switched capacitor circuits. Standard NOC generator circuits available in the literature uses delay circuits realized using simple inverters connected in a chain. For moderate frequencies, the number of inverters required for a reasonable non-overlapping period is nominal; however, for low frequency applications such as bio-medical signal processing, the number could be quite large. This affects the area and power budget of the design. In this work it is proposed to use inverters in inverted form to realize significant delay with less number of transistors. Simulation results suggest that the proposed circuit will be area and power efficient as compared to the conventional NOC circuits.

Non Overlapping Clock generator for switched capacitor circuits in Bio-Medical applications

Switched capacitor circuits have become a popular method for implementing mixed signal blocks in standard CMOS technologies. Non-Overlapping Clock (NOC) generator is a key building block of switched capacitor circuits. Standard NOC circuits use simple inverters to realize delays. For high to moderate frequencies, the number of inverters required is nominal. But for low frequency applications like Bio-Medical Signal Processing, the number of inverters increase drastically affecting the area and power budget. In this work it is proposed to use an inverter in inverted form along with a simple inverter as an inverting circuit to realize significant delay with lesser number of transistors. Simulation results suggest that the proposed inverter is area and power efficient.

Design of folded cascode opamp using Potential Distribution Method

In this work, design of CMOS opamps using Potential Distribution Method (PDM) is discussed. PDM is a newly proposed device sizing technique for analog circuits based on voltage distribution at different nodes. This technique is free from complex mathematical expressions governing the devices and the circuit. Instead of relying on analytical design approach, PDM directly utilizes the simulator as a device sizing tool to meet the target specifications. This is achieved by first designing the circuit with moderate performance by logically or uniformly allocating node voltages and then modifying these node potentials to meet the target specifications. PDM is also technology independent and can be applied to both, long and short channel devices. A fully differential folded cascode opamp is then designed using PDM. Dependency of response of the opamp on different node voltages is discussed. It is shown how PDM can be employed to fine tune the opamps response to meet the specifications and the simulation results are presented.

Low Frequency Ring Oscillator and Its Use in Non Overlapping Clock Generation

Switched capacitor (SC) techniques have become the default standard for implementing mixed signal blocks in CMOS technologies. Non-overlapping clock (NOC) generator is a key building block for SC circuits, traditionally implemented using inverter chains. For moderate and high frequencies, the numbers of inverter stages are nominal. But for low frequency applications, like biomedical signal processing, the numbers of inverters increase significantly affecting the area and power budget of the design. In this work, three new inverter cells are proposed for realizing low frequency ring oscillator. They exhibit a delay larger than other popular implementation techniques. Simulation results show that low frequency oscillations can be achieved with much lesser number of transistors and with lower power dissipation. The proposed inverter is then used to realize a voltage controlled NOC generator whose non-overlap period can be modulated. Alternate digital multiplexing technique is also presented to control the non-overlap period.

Simplified design method for fully differential gain-boosted folded cascade OTA

Operational amplifiers are an integral part of analog and mixed signal design. With the advancement of process technology, the transistor dimensions are rapidly scaling down leading to reduced ro. In deep sub-micron regime, this leads to a fairly small low frequency gain offered by amplifiers. Applications demanding high gain amplifiers suffer at design level. Even multi-stage architectures fail to provide gain greater than 60 dB. Designers now have to depend on alternate techniques like gain boosting architectures. For most designers, designing gain boosting structures using traditional design method become a trivial problem. They often find it difficult to keep all transistors in saturation, particularly in cascode structures. In this work, a simplified design method for designing a fully differential gain boosted folded cascode amplifier is presented. Potential Distribution Method (PDM) guarantees that all transistors are operating in saturation region. PDM is an extremely simple and quick methodology, which is independent of process technology, device length and complex equations governing the devices and the circuit. The implemented design provides a DC gain of around 118 dB with a unity gain frequency of 183 MHz. The design is carried out using UMC 180 nm CMOS technology and the simulation results are presented.

Design of DXT architecture using current switched integrator

This paper describes a sampled analog architecture to compute discrete linear transforms, DXT(X=C/H/S/F), using switched capacitor blocks fed with current samples. The scheme uses matrix representation of any DXT kernel, and multiplies each column of the kernel matrix with the input samples simultaneously, using an array of current scalers. It is shown that current scalers can be used to perform multiplication, suiting the needs of DXT computation. Multiplied columns are then fed to different integrators by means of a cross-switch to perform recursive summation. The proposed current input switched capacitor integrator performs current domain multiplication, which leads to more linear and accurate design as compared to resistor or capacitor based scheme.