Ashish Rai Shrivastava

Implementing OpenMP on a high performance embedded multicore MPSoC

In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model such as OpenMP has the potential to increase programmer productivity, reducing the design/development costs and time to market for such systems. However, OpenMP needs to be extended if it is to meet the needs of embedded application developers, who require the ability to express multiple levels of parallelism, real-time and resource constraints, and to provide additional information in support of optimization. It must also be capable of supporting the mapping of different software tasks, or components, to the devices configured in a given architecture.

Quantization analysis tool for fixed-point implementation of real time algorithms on the TMS320C5000

Digital Signal Processing (DSP) chips are getting faster, with higher available performance and lower power consumption. Simultaneously, the complexity of algorithms that are being implemented on these devices is increasing rapidly. Currently, Texas Instruments (TI) has targeted the TMS320C5000, fixed point (16 bits), family of DSPs to be the most power efficient DSP engine. Implementing complex algorithms on a fixed-point platform is not a trivial task. Fixed-point programs require variables to have a quantization format, and prevent (minimize) overflow and underflow quantization errors The process of converting a successful floating-point implementation of an algorithm to fixed-point can be a long and tedious process. This paper presents software tool (Fast Quantization Tool (FaQT)), which simplifies the process of converting an algorithm from floating-point to fixed-point. The paper also presents the application of FaQT to a Noise Reduction (NR) algorithm used in speech processing for cell-phone and other audio applications.

A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS

A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.