Duc Quang Bui

A 600-MHz VLIW DSP

A 600 MHz VLIW DSP, which implements the C64x VelociTI.2/spl trade/ architecture delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates at 0.3 mW/MMAC (16 b). The chip has 64 M transistors and dissipates 718 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and 0.9 V. It has an 8-way VLIW DSP core, a 2-level memory system, and 2.4 GB/s I/O bandwidth. The DSP chip is implemented in 0.13 μm CMOS technology with 6-layer copper metalization.

A 1.25GHz 0.8W C66x DSP Core in 40nm CMOS

The next-generation C66x DSP integrated fixed and floating-point DSP implemented in TSMC 40nm process is presented in this paper. The DSP core runs at 1.25GHz at 0.9V and has a standby power consumption of 800mW. The core transistor count is 21.5 million. The DSP core features 8-way VLIW floating point Data path and a two level memory system and delivers 40 GMACS or 10 GFLOPS floating point MAC performance at 1.25GHz.

A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS

A next generation VLIW DSP Central Processing Unit (CPU) which has an integrated fixed point and floating point Instruction Set Architecture (ISA) is presented. It is designed to meet a 1.5 GHz core clock frequency in a 40nm process with aggressive area and power goals. In this paper, the benchmarking process and benefits of newly defined instructions such as complex matrix multiply is explained. Also, the CPU data path is described in detail, highlighting several novel micro-architecture features. Finally, our design methodology as well as verification methodology to ensure functional correctness utilizing formal equivalent verification is described.

Heterogeneous Multi-processor Coherent Interconnect

The rapid increase in processor and memory integration onto a single die continues to place increasingly complex demands on the interconnect network. In addition to providing low latency, high speed and high bandwidth access from all processors to all shared resources, the burdens of hardware cache coherence and resource virtualization are being placed upon the interconnect as well. This paper describes a multi-core shared memory controller interconnect (MSMC) which supports up to 12 processors, 8 independent banks of IO-coherent on-chip shared RAM, an IO-coherent external memory controller, and high bandwidth IO connections to the SoC infrastructure. MSMC also provides basic IO address translation and memory protection for the on-chip shared SRAM and external memory as well as soft error protection with hardware scrubbing for the on-chip memory. MSMC formed the heart of the compute cluster for a 28-nm CMOS device including 8 Texas Instruments C66x DSP processors and 4 cache-coherent ARM A15 processors sharing 6 MB of on-chip SRAM running at 1.3 Ghz. At this speed MSMC provides all connected masters a combined read/write bandwidth of nearly 1TB/s to access a combined read/write bandwidth of 457.6 GB/s to all shared resources @ 16 mm2.