Assaf Lahav

Kirana: a solid-state megapixel uCMOS image sensor for ultrahigh speed imaging

This paper describes a solid-state sensor for ultra-high-speed (UHS) imaging. The ‘Kirana’ sensor was designed and manufactured in a 180 nm CMOS technology to achieve full-frame 0.7 Megapixel video capture at speeds at 2 MHz. The 30 μm pixels contain a pinned photodiode, a set of 180 low-leakage storage cells, a floating-diffusion, and a source follower output structure. Both the individual cells and the way they are arranged in the pixel are novel. The pixel architecture allows correlated double sampling for low noise operation. In the fast mode, the storage cells are operated as a circular buffer, where 180 consecutive frames are stored until receipt of a trigger; up to 5 video-bursts per second can be read out. In the ‘slow’ mode, the storage cells act like a pipeline; the sensor can be read out like a conventional sensor at a continuous frame rate of 1,180 fps. The sensor architecture is fully scalable in resolution since memory cells are located inside each pixel. The pixel architecture is scalable in memory depth (number of frames) as a trade-off with pixel size, dependent on application. The present implementation of 0.7 Mpixels has an array focal plane which is optimized for standard 35 mm optics, whilst offering a competitive 180-frame recording depth. The sensor described has been manufactured and is currently being characterized. Operation of the sensor in the fast mode at 2 million frames per second has been achieved. Details on the camera/sensor operation are presented together with first experimental results.

A Fast-Gated CMOS Image Sensor With a Vertical Overflow Drain Shutter Mechanism

This paper presents a fast-gated CMOS image sensor (CIS) with a vertical overflow drain (VOD) shutter mechanism. The prototype imager includes two novel features: 1) the adaptation of the VOD shutter structure into a 0.18-μm CIS process and 2) the application of the VOD shutter for the purposes of time-resolved imaging with down to 5-ns pulsewidth. A 360-pixel × 180-pixel array with several 5.4-μm × 5.4-μm pixel types was implemented and tested, demonstrating 2-ns shutter rise/fall times and the 1:20 shutter contrast ratio for 850-nm pulsed illumination. These parameters, together with the uniformity of the shutter and the large full-well capacity of the pixel, are on par with the state-of-the-art of indirect time-of-flight and time-resolved imagers. The device structure and the special mode of operation that enables a fast gating are studied through the TCAD simulations and experimental results. Important design features that affect the pixel performance are illustrated in detail.

Development of a ToF Pixel With VOD Shutter Mechanism, High IR QE, Four Storages, and CDS

In this paper we discuss the development of an indirect time-of-flight (ToF) pixel in the 0.11-μm CMOS image sensor technology. The pixel design is based on a pinned-photodiode structure with a novel vertical overflow drain (VOD) shutter mechanism used for fast modulation. We present the second generation of the pixel, with a greatly improved VOD structure that enables a fast shutter efficiency better than 1:100 and a deeper photodiode collection depth for better quantum efficiency in the near-infrared wavelengths. We present a new 6.7-μm pixel design with four pinned storage diodes (SDs) that feature in-pixel complete charge transfer and enable correlated-double-sampling readout as well as an almost simultaneous global shutter exposure of up to four interleaved frames to be used for the scene depth computation. The novel design features a low readout noise of 7.5e-and a full-well-capacity of 9500eper SD (a total of 38000eper pixel).

Backside illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensors

Abstract This chapter reviews modern manufacturing techniques for backside illuminated (BSI) CMOS image sensors (CISs). It presents a thorough discussion regarding the advantages and disadvantages of the front illuminated CIS throughout different CMOS fabrication nodes and introduces a historical review, state-of-the-art discussion on the technological issues as well as on the applications and performance of back illuminated imagers. The chapter discusses all the relevant state-of-the-art issues of the imagers in both, commercial applications and high-performance scientific and industrial niche applications.