Amos Fenigstein

Kirana: a solid-state megapixel uCMOS image sensor for ultrahigh speed imaging

This paper describes a solid-state sensor for ultra-high-speed (UHS) imaging. The ‘Kirana’ sensor was designed and manufactured in a 180 nm CMOS technology to achieve full-frame 0.7 Megapixel video capture at speeds at 2 MHz. The 30 μm pixels contain a pinned photodiode, a set of 180 low-leakage storage cells, a floating-diffusion, and a source follower output structure. Both the individual cells and the way they are arranged in the pixel are novel. The pixel architecture allows correlated double sampling for low noise operation. In the fast mode, the storage cells are operated as a circular buffer, where 180 consecutive frames are stored until receipt of a trigger; up to 5 video-bursts per second can be read out. In the ‘slow’ mode, the storage cells act like a pipeline; the sensor can be read out like a conventional sensor at a continuous frame rate of 1,180 fps. The sensor architecture is fully scalable in resolution since memory cells are located inside each pixel. The pixel architecture is scalable in memory depth (number of frames) as a trade-off with pixel size, dependent on application. The present implementation of 0.7 Mpixels has an array focal plane which is optimized for standard 35 mm optics, whilst offering a competitive 180-frame recording depth. The sensor described has been manufactured and is currently being characterized. Operation of the sensor in the fast mode at 2 million frames per second has been achieved. Details on the camera/sensor operation are presented together with first experimental results.

C-Flash: An Ultra-Low Power Single Poly Logic NVM

An ultra-low power logic NVM has currents <10 nA/cell in all operating regimes, high programming/erase speeds, excellent endurance/retention and allows strong Vdd fluctuations. The memory uses CMOS inverter read-out principle (C-Flash) and F-N injection for programming and erase with voltages below +5 V. The memory is intended for RFID and advanced mobile applications requiring small/middle sized embedded memory modules.

Dead Time Compensation in CMOS Single Photon Avalanche Diodes With Active Quenching and External Reset

Single photon avalanche diodes (SPADs) in CMOS are becoming increasingly interesting devices for timing applications, such as fluorescence lifetime imaging, positron emission tomography, and time of flight mass spectroscopy. The CMOS allows integration of functionalities like time-to-digital converters within the same pixel, and the manufacturing of large format arrays. Dead time has to be taken into account in order to correctly interpret SPAD measurements. In this paper, we derive and test a model for dead time in real SPADs where reset is generated off-pixel. We test the model using our own custom designed devices made in a low-voltage 180-nm CMOS image sensor process with full custom implants. A Monte Carlo simulation is implemented to compare with experimental results. Using a fitting method, higher values of the photon detection efficiency (PDE) can be extracted than with a simple linear fit. The resulting PDE corrections are significant, up to 100% depending on the conditions. The limitations are approximated, and it is found that accurate predictions of the true count rate are possible over a control range of 0.25-1.0 MHz.

Transition to second-generation HgCdTe FPA

The transition to second generation backside-illuminated dense LWIR FPAs requires consideration of issues not previously relevant in first generation modules: unlike in front illuminated arrays, the MTF (or effective area) of a pixel is no longer close to the ideal sinc function. The cutoff wavelength, quantum efficiency and crosstalk depend on the thickness and composition grading of the epitaxial layer. The tradeoff between resolution and sensitivity demands extensive engineering and optimization of the array configuration. The transition was accomplished by comparisons of simulations with experimental results. Expectations of performance indicators, such as MTF, quantum efficiency and crosstalk were obtained by detailed Monte-Carlo simulations. The results were used to configure the focal plane array. This paper discuses the basic assumptions and simulation results and compares them with the performance of actual detectors and various test structures.

Development of a ToF Pixel With VOD Shutter Mechanism, High IR QE, Four Storages, and CDS

In this paper we discuss the development of an indirect time-of-flight (ToF) pixel in the 0.11-μm CMOS image sensor technology. The pixel design is based on a pinned-photodiode structure with a novel vertical overflow drain (VOD) shutter mechanism used for fast modulation. We present the second generation of the pixel, with a greatly improved VOD structure that enables a fast shutter efficiency better than 1:100 and a deeper photodiode collection depth for better quantum efficiency in the near-infrared wavelengths. We present a new 6.7-μm pixel design with four pinned storage diodes (SDs) that feature in-pixel complete charge transfer and enable correlated-double-sampling readout as well as an almost simultaneous global shutter exposure of up to four interleaved frames to be used for the scene depth computation. The novel design features a low readout noise of 7.5e-and a full-well-capacity of 9500eper SD (a total of 38000eper pixel).

Extending endurance of NROM memories to over 10 million program/erase cycles

We report on NROM (nitride read only) memory with enhanced endurance/retention. A novel “refresh” is introduced into the cycling algorithm to exclude parasitic electron trapping in the memory transistor. Negative gate pulses are applied when the drain voltage in the erase procedure reaches the threshold value. The memory stack is optimized to allow injection of holes from the substrate through the bottom oxide (BOX). More than 10 million program/erase (P/E) cycles with excellent retention are easily achieved.