Yakov Roizin

Novel techniques for data retention and Leff measurements in two bit microFLASH® memory cells

The paper describes original techniques developed to characterize Tower Semiconductor Ltd. microFLASH® memory that features two bits per cell. In the microFLASH® transistors electrons are stored in the ONO (oxide-nitride-oxide) stack at the edges of the channel. Charge migration in the ONO along the channel is responsible for data retention in this case. The idea of the proposed retention control technique is to block the source and drain regions of an ONO transistor channel by trapping the electrons and then to force current parallel to source and drain. A new test structure (H-transistor) was designed according to these principles. The technique allows monitoring the position of trapped electrons and registering their shifting in the channel after high temperature bakes. Effective channel length (Leff) is critical for the discussed memory. Leff is extracted from C-V measurements. Special test structures were designed and fabricated for these purposes. The structures simulate the real memory array geomet...

Density functional theory study of deep traps in silicon nitride memories

Using density functional theory, the interaction of hydrogen with a nitrogen vacancy in β-Si3N4 is investigated. A single H atom was found to be energetically favorable over non- and doubly protonated vacancies. The traps composed of excess silicon and hydrogen have negative correlation energy which is connected with different distances of Si–H and Si–Si bonds in charged and neutral states. The energy gains after trapping are consistent with trap activation energies in advanced silicon nitride memories. Based on the present results, a model of memory traps is proposed.

SiO2∕Si3N4∕Al2O3 stacks for scaled-down memory devices: Effects of interfaces and thermal annealing

Effects of interfaces and thermal annealing on the electrical performance of the SiO2∕Si3N4∕Al2O3 (ONA) stacks in nonvolatile memory devices were investigated. The results demonstrated the principal role of Si3N4∕Al2O3 and Al2O3/metal-gate interfaces in controlling charge retention properties of memory cells. Memory devices that employ both electron and hole trappings were fabricated using a controlled oxidation of nitride surface prior to the Al2O3 growth, a high-temperature annealing of the ONA stack in the N2+O2 atmosphere, and a metal gate electrode having a high work function (Pt). These devices exhibited electrical performance superior to that of their existing SiO2∕Si3N4∕SiO2 analogs.

C-Flash: An Ultra-Low Power Single Poly Logic NVM

An ultra-low power logic NVM has currents <10 nA/cell in all operating regimes, high programming/erase speeds, excellent endurance/retention and allows strong Vdd fluctuations. The memory uses CMOS inverter read-out principle (C-Flash) and F-N injection for programming and erase with voltages below +5 V. The memory is intended for RFID and advanced mobile applications requiring small/middle sized embedded memory modules.

Radiation Tolerance of NROM Embedded Products

Radiation tolerance of NROM memories is demonstrated at the level of industrial 4 Mbit memory embedded modules, specifically not designed for operation in radiation harsh environments. The memory fabricated in 0.18 um technology remains fully functional after total ionization doses exceeding 100 krad. The tests were performed by irradiating with γ-rays ( 60Co source) and 10 MeV 11B ions in active (during programming/erase and read-out) and passive (no bias) modes. Comprehensive statistics were obtained by using large memory arrays and comparison of the data with the parameters of irradiated single cells allowed deep understanding of the physical phenomena in the irradiated NROM devices for both moderate (<;1 Mrad) and large (> 1 Mrad) TID. The obtained data is currently employed in the design of the new generation of NROM memories, having improved radiation tolerance.

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

The key factor in widespread adoption of Radio Frequency Identification (RFID) technology is tag cost minimization. This paper presents the first low-cost, ultra-low power, passive RFID tag, fully integrated on a single substrate in a standard CMOS process. The system combines a 24 GHz, dual on-chip antenna, RF front-end, and a C-Flash based, rewritable, non-volatile memory module to achieve full on-chip system integration. The complete system was designed and fabricated in the TowerJazz 0.18 μm CMOS technology without any additional mask adders. By embedding the RF, memory, and digital components together upon a single substrate in a standard digital process, the low-cost aspirations of the “5-cent RFID tag” become feasible. Design considerations, analysis, circuit implementations, and measurement results are presented. The entire system was fabricated on a 3.6 mm × 1.6 mm (6.9 mm2) die with the integrated antennas comprising 82% of the silicon area. The total read power was measured to be 13.2 μW, which is sufficiently supplied by the on-chip energy harvesting unit.

Structure, Chemistry, and Electrical Performance of Silicon Oxide-Nitride-Oxide Stacks on Silicon

The structure and chemistry of silicon oxide-nitride-oxide (ONO) stacks on silicon with differently processed top oxide layers were analyzed using high-resolution transmission electron microscopy, electron energy loss spectroscopy, secondary ion mass spectroscopy, and X-ray specular reflectometry. The changes observed in the structure and chemistry of the ONO stacks were correlated with the electrical performance of these stacks in flash-memory devices. The results demonstrated that using larger thermal budgets to form the top oxide layer yields (i) broader N distribution across the nitride/oxide interfaces, (ii) reduced H content at the Si/SiO 2 interfaces, (iii) increased density of the top oxide layer, and ultimately, (iv) improved electrical performance of ONO-based memory devices.

Non-volatile memory transistor based on Pt nanocrystals with negative differencial resistance

We report on the structural and electrical characteristics of non-volatile memory (NVM) transistors and capacitors that use Pt nanocrystals (NCs) for charge storage. The transistor exhibits a memory window of 0.6 V for a sweep of ±2.5 V which increases to 11.5 V at ±10 V. The trapped charges (electron and hole) density for a ±10 V write/erase signal are 2.9 × 1013 cm−2. At small source to drain voltages (VSD) and for delay times longer than 0.1 ms, negative differential resistance (NDR) type behavior of the transistor source to drain ISD-VSD characteristics is revealed. The physical mechanism responsible for the NDR is related to the dynamics of electron injection (by tunneling through the thin bottom oxide) and their trapping by the Pt NCs. The large storage capability and relatively low program/erase voltages as well as the use of Pt, that is a Fab friendly material, make the described NVM transistors promising for practical applications.

Interface states in cycled hot electron injection program∕hot hole erase silicon–oxide-nitride–oxide–silicon memories

Charge pumping measurements were performed to characterize the interface between silicon and bottom oxide in silicon–oxide-nitride–oxide–silicon memory transistors, where information is stored as charges in nitride at the edges of the channel. The charge pumping signal was found to strongly increase with the number of performed program∕erase cycles, thus indicating the creation of traps with a density on the order of 1012cm−2 (after 100 000 cycles). To estimate the length of the degraded region, the charge pumping signal dependence on the drain voltage was compared with the simulated drain depletion length using TSUPREM∕Medici software. The damaged length calculated from the metallurgical junction is about 200A at the beginning of the endurance test and increases to 500A after 100 000 cycles.

Ionizing Radiation Effects on Non Volatile Read Only Memory Cells

Threshold voltage (<i>V</i>_th) and drain-source current (<i>I</i>_DS) behaviour of nitride read only memories (NROM) were studied both in situ during irradiation or after irradiation with photons and ions. <i>V</i>_th loss fluctuations are well explained by the same Weibull statistics regardless of the irradiation species and total dose. Results of drain current measurements in-situ during irradiation with photons and ions reveal a step-like increase of <i>I</i>_DS with the total irradiation dose. A brief physical explanation is also provided.