Assaf Shappir

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.

4-bit per cell NROM reliability

The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme

Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices

Abstract An analytical model is presented for the subthreshold slope degradation of localized-charge-trapping based non-volatile memory devices. The model incorporates fringing field effects and asserts that the subthreshold slope degradation is a distinct characteristic of localized-charge-trapping. Results are compared with experimental data and two-dimensional simulations performed on an NROM™ non-volatile memory cell. These substantiate that generation of interface states is not the primary cause of the discussed phenomenon and indicate that channel-hot-electron injection takes place mostly in a narrow region at the drain junction, with a ∼20 nm tail above the transistor channel. This implies that the localization concept does not impair the scalability of NROM™, two physical bits per cell, technology.

The two-bit NROM reliability

Saifun NROM/spl trade/ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM technology is able to provide code flash, data flash, embedded flash, and true EEPROM functionality with a single fabrication process and minor architectural adjustments. Reliability topics of NROM technology are discussed, focusing on the ability to achieve 10-year data retention after 10/sup 5/ program and erase cycles. The accumulated knowledge of NROM physics allows this technology to successfully compete with the industry standard floating-gate memory technology and to gain the acceptance of the memory market.

Traps spectroscopy of the Si3Ni4 layer using localized charge-trapping nonvolatile memory device

A spectroscopy method is proposed and implemented for Si3Ni4 layer using the NROM® cell and the gate-induced-drain-leakage measurement. The proposed method allows probing of both electron and hole traps in the entire band gap with almost no fitting parameters. The energy levels of occupied charge traps are extracted following a thermionic emission model. It is found that the peak energy distribution of the electron traps is located ∼2.2eV below the nitride conduction band with a full width at half maximum (FWHM) of 0.16eV, while the peak energy distribution of the hole traps is located ∼1.5eV above the nitride valence band with a FWHM of 0.64eV. Based on these results, the retention loss of the NROM cell is successfully predicted over a wide range of temperatures and time scales.

Unified retention model for localized charge trapping nonvolatile memory device

Retention after cycling in an NROM nonvolatile memory cell is investigated. Electrical characterizations combined with two-dimensional simulations were employed. By combining subthreshold current characterizations with gate-induced drain leakage measurements, the retention loss mechanisms are quantified and differentiated. A unified retention model for the NROM technology is proposed, incorporating both lateral charge transport in the nitride layer and hot carrier-induced interface-states formation. The fabrication conditions in the various studies reported in the literature and the resultant impact on interface-states formation are most likely the cause of the formally nonresolved debate regarding the origin of retention loss in NROM technology.

Relaxation of localized charge in trapping-based nonvolatile memory devices

Relaxation dynamics of trapped holes and trapped electrons in the ONO layer of NROM devices is studied. Hole relaxation is eight orders of magnitude faster than electron relaxation. The degradation of data retention in cycled NROM cells is interpreted in terms of dispersive transport arising from random-walk of excess holes in the disordered nitride glass.

Interface states formation in a localized charge trapping nonvolatile memory device

Two NROM nonvolatile memory devices that are practically identical but exhibit different postcycling characteristics are investigated. Electrical characterizations combined with two-dimensional drift diffusion simulations were employed to quantify and differentiate the retention loss mechanisms. The comparison demonstrates the coexistence of two retention loss mechanisms, lateral charge transport in the nitride layer, and hot carrier induced interface states formation and anneal. The fabrication conditions in the various studies reported in the literature and the resultant impact on interface states formation are most likely the cause of the formally nonresolved debate regarding the origin of retention loss in NROM technology. The reduction in interface state formation during cycling is a key to achieving high reliability NROM cells and products.

Charge Loss Mechanisms in a Localized Trapping Based Nonvolatile Memory Device

In this work, quantification of the theories and models attributed to the NROM cell Vt decay and the dominant charge loss mechanism dictating this phenomenon are discussed. The main objective is to determine whether the transport of the localized trapped charge is mainly lateral within the nitride layer or vertical back to the silicon substrate. Electrical characterizations and analytic modeling are employed for comparison of theories.

Spatial characterization of hot carriers injected into the gate dielectric stack of a MOSFET based non-volatile memory device

Subthreshold slope degradation in the NROM/spl trade/ localized-charge-trapping non-volatile memory device is utilized to investigate the spatial distributions of hot carriers injected into the gate dielectric stack. An analytical model is presented, which attributes the subthreshold slope degradation to the formation of a fringing field induced extended depletion layer. It is shown that electron and hole trapping takes place mostly in a narrow, 40-50 nm wide, region near the drain junction.