Eli Lusky

Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/ device

Channel hot electron (CHE) injection, is widely used as main programming method in flash products. The spatial distribution could only be measured indirectly through stress-based experiments. A simple measurement technique to spatially characterize CHE injection is presented. It is shown that subthreshold slope degradation during programming of NROM/sup TM/ device provides the location and distribution of the injected electrons. It is shown that injection takes place mostly above the drain region and thus, results in subthreshold slope degradation. It is further shown, based on two-dimensional modeling, that charge distribution width is narrower than 40 nm.

Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric

An electrons retention model for localized charge, trapped in ONO stacked dielectric, is introduced utilizing the nitride read-only memory (NROM) device. The observed reduction in threshold voltage (retention loss) of a programmed cell is explained in terms of lateral charge redistribution in the nitride layer. Assuming a thermal emission mechanism, the energy levels of the electrons traps were extracted and found to be distributed continuously in the nitride band gap, with a median value of /spl sim/2.12 eV below the conduction band. Utilizing these findings, the model allows a prediction of the retention loss over wide range of temperatures, between 140/spl deg/C-300/spl deg/C, long times, up to 10/sup 7/ s, large retention loss levels, /spl sim/90%, and programming windows, 1.9-3.3 V. Based on this work the ten-year relative retention loss at 140/spl deg/C of an NROM cell is expected to be 14% (V/sub DS/=0.1 V) and the equivalent uncycled product loss is expected to be 8%.

Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells

The aim of this paper is to achieve a correct description of the programming charge distribution in NROM memory devices. This is essential to prove device functionality and to extrapolate scaling limits of devices. For this purpose we employ an inverse modeling based methodology using measurements easily performed, such as subthreshold characteristics and threshold voltage measurements. We show a simple model of programming charge distribution that can be easily implemented in two-dimensional (2-D) TCAD simulations. Results show good agreement between measured and simulated currents under different bias conditions and for different programming levels.

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.

4-bit per cell NROM reliability

The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme

Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices

Abstract An analytical model is presented for the subthreshold slope degradation of localized-charge-trapping based non-volatile memory devices. The model incorporates fringing field effects and asserts that the subthreshold slope degradation is a distinct characteristic of localized-charge-trapping. Results are compared with experimental data and two-dimensional simulations performed on an NROM™ non-volatile memory cell. These substantiate that generation of interface states is not the primary cause of the discussed phenomenon and indicate that channel-hot-electron injection takes place mostly in a narrow region at the drain junction, with a ∼20 nm tail above the transistor channel. This implies that the localization concept does not impair the scalability of NROM™, two physical bits per cell, technology.

The two-bit NROM reliability

Saifun NROM/spl trade/ is a novel localized charge-trapping-based nonvolatile memory technology that employs inherent two-bits-per-cell operation. NROM technology is able to provide code flash, data flash, embedded flash, and true EEPROM functionality with a single fabrication process and minor architectural adjustments. Reliability topics of NROM technology are discussed, focusing on the ability to achieve 10-year data retention after 10/sup 5/ program and erase cycles. The accumulated knowledge of NROM physics allows this technology to successfully compete with the industry standard floating-gate memory technology and to gain the acceptance of the memory market.

Traps spectroscopy of the Si3Ni4 layer using localized charge-trapping nonvolatile memory device

A spectroscopy method is proposed and implemented for Si3Ni4 layer using the NROM® cell and the gate-induced-drain-leakage measurement. The proposed method allows probing of both electron and hole traps in the entire band gap with almost no fitting parameters. The energy levels of occupied charge traps are extracted following a thermionic emission model. It is found that the peak energy distribution of the electron traps is located ∼2.2eV below the nitride conduction band with a full width at half maximum (FWHM) of 0.16eV, while the peak energy distribution of the hole traps is located ∼1.5eV above the nitride valence band with a FWHM of 0.64eV. Based on these results, the retention loss of the NROM cell is successfully predicted over a wide range of temperatures and time scales.

Charge Loss Mechanisms in a Localized Trapping Based Nonvolatile Memory Device

In this work, quantification of the theories and models attributed to the NROM cell Vt decay and the dominant charge loss mechanism dictating this phenomenon are discussed. The main objective is to determine whether the transport of the localized trapped charge is mainly lateral within the nitride layer or vertical back to the silicon substrate. Electrical characterizations and analytic modeling are employed for comparison of theories.