Ilan Bloom

NROM: A novel localized trapping, 2-bit nonvolatile memory cell

This paper presents a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation. It is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction. Programming is performed by channel hot electron injection and erase by tunneling enhanced hot hole injection. The new read methodology is very sensitive to the location of trapped charge above the source. This single device cell has a two physical bit storage capability. The cell shows improved erase performances, no over erase and erratic bit issues, very good retention at 250/spl deg/C, and endurance up to 1M cycles. Only four masks are added to a standard CMOS process to implement a virtual ground array. In a typical 0.35 /spl mu/m process, the area of a bit is 0.315 /spl mu/m/sup 2/ and 0.188 /spl mu/m/sup 2/ in 0.25 /spl mu/m technology. All these features and the small cell size compared to any other flash cell make this device a very attractive solution for all NVM applications.

1/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation

A new experimental setup for the study of 1/ f noise of metal‐oxide‐semiconductor transistor under nonsteady state conditions is presented. The noise measurements demonstrate for the first time that, by interposing periods of negative bias corresponding to accumulation between the monitored periods of positive bias corresponding to inversion, the low‐frequency noise sampled in the positive bias intervals is reduced.

Characterization of channel hot electron injection by the subthreshold slope of NROM/sup TM/ device

Channel hot electron (CHE) injection, is widely used as main programming method in flash products. The spatial distribution could only be measured indirectly through stress-based experiments. A simple measurement technique to spatially characterize CHE injection is presented. It is shown that subthreshold slope degradation during programming of NROM/sup TM/ device provides the location and distribution of the injected electrons. It is shown that injection takes place mostly above the drain region and thus, results in subthreshold slope degradation. It is further shown, based on two-dimensional modeling, that charge distribution width is narrower than 40 nm.

Electrons retention model for localized charge in oxide-nitride-oxide (ONO) dielectric

An electrons retention model for localized charge, trapped in ONO stacked dielectric, is introduced utilizing the nitride read-only memory (NROM) device. The observed reduction in threshold voltage (retention loss) of a programmed cell is explained in terms of lateral charge redistribution in the nitride layer. Assuming a thermal emission mechanism, the energy levels of the electrons traps were extracted and found to be distributed continuously in the nitride band gap, with a median value of /spl sim/2.12 eV below the conduction band. Utilizing these findings, the model allows a prediction of the retention loss over wide range of temperatures, between 140/spl deg/C-300/spl deg/C, long times, up to 10/sup 7/ s, large retention loss levels, /spl sim/90%, and programming windows, 1.9-3.3 V. Based on this work the ten-year relative retention loss at 140/spl deg/C of an NROM cell is expected to be 14% (V/sub DS/=0.1 V) and the equivalent uncycled product loss is expected to be 8%.

1/f Noise in CMOS transistors for analog applications from subthreshold to saturation

Abstract Detailed noise measurements of the 1/ f noise in p - and n -mos transistors for analog applications are reported under various bias conditions ranging from subthreshold to saturation. The CMOS transistors under study have a relatively large area, exhibit long channel behavior and are fabricated in a commercial “low noise process”, as prescribed for analog applications. A clear methodology and useful models for the power spectral densities of the gate voltage and drain current are presented and are based on recent studies in sub-micron transistors that have established the physical origin of 1/ f noise in MOS transistors. In saturation, it is found that it is advisable to limit the bias voltages to values that are experimentally determined from the transconductance characteristics and correspond to a nearly constant channel mobility. The experimentally observed reduction in channel mobility indicates the existence of strong fields that induce additional oxide charging and hence an increase in the effective density of oxide traps and the noise. In the bias voltages where channel mobility is nearly constant, the measured input-referred noise power is practically constant. Below threshold voltage, a reduction is observed in the input-referred noise as gate voltage is decreased, corresponding to the prediction of the model and due to the exponential reduction of the inversion capacitance with gate voltage. This behavior is observed for both n -mos and p -mos transistors.

Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells

The aim of this paper is to achieve a correct description of the programming charge distribution in NROM memory devices. This is essential to prove device functionality and to extrapolate scaling limits of devices. For this purpose we employ an inverse modeling based methodology using measurements easily performed, such as subthreshold characteristics and threshold voltage measurements. We show a simple model of programming charge distribution that can be easily implemented in two-dimensional (2-D) TCAD simulations. Results show good agreement between measured and simulated currents under different bias conditions and for different programming levels.

Investigation of channel hot electron injection by localized charge-trapping nonvolatile memory devices

A novel measurement method to extract the spatial distribution of channel hot electron injection is described. The method is based on characterization of localized trapped-charge in the nitride read-only memory (NROM) device. The charge distribution is determined by iteratively fitting simulated subthreshold and gate induced drain leakage (GIDL) currents to measurements. It is shown that the subthreshold and the GIDL measurements are sensitive to charge trapped over the n+ junction edge. Their characteristics are determined by the trapped charge width, density and location and the associated fringing field. Extremely high sensitivity of the GIDL measurement to localized charge over the n+ junction is demonstrated. The extracted charge distribution width is shown to be /spl sim/40 nm, located over the junction edge.

4-bit per cell NROM reliability

The realization of a 4-bit NROM cell is possible due to the two physically separated bits on each side of the cell. Only 4 Vt levels on each bit are required. Key features of a 4-bit product are optimized technology, accurate and fast programming algorithm (3MB/s write speed), no single bit failures and window sensing with moving reference as an error detection and correction scheme

Subthreshold slope degradation model for localized-charge-trapping based non-volatile memory devices

Abstract An analytical model is presented for the subthreshold slope degradation of localized-charge-trapping based non-volatile memory devices. The model incorporates fringing field effects and asserts that the subthreshold slope degradation is a distinct characteristic of localized-charge-trapping. Results are compared with experimental data and two-dimensional simulations performed on an NROM™ non-volatile memory cell. These substantiate that generation of interface states is not the primary cause of the discussed phenomenon and indicate that channel-hot-electron injection takes place mostly in a narrow region at the drain junction, with a ∼20 nm tail above the transistor channel. This implies that the localization concept does not impair the scalability of NROM™, two physical bits per cell, technology.

NROM TM --a new technology for non-volatile memory products

Abstract NROM TM ––is a new technology for non-volatile memories (NVMs); it offers three major improvements relative to the Floating Gate technology: one technology for all NVM products (Flash, EEPROM, ROM and Embedded), higher density (2.5 F 2 /bit in Flash, where F is the feature size of the process), and simpler process with reduced number of masks without any “exotic” materials. The NROM TM cell is based on localized charge trapping above the junction edge, storing two physically separated bits per cell. Performance of new NVM NROM TM based products show endurance up to 100 K with retention of 10 years at 150 °C.