Assim Boukhayma

Temporal Readout Noise Analysis and Reduction Techniques for Low-Light CMOS Image Sensors

In this paper, an analytical noise calculation is presented to derive the impact of process and design parameters on 1/f and thermal noise for a low-noise CMOS image sensor (CIS) readout chain. It is shown that dramatic noise reduction is obtained by using a thin-oxide transistor as the source follower of a typical 4T pixel. This approach is confirmed by a test chip designed in a 180-nm CIS process and embedding small arrays of the proposed new pixels together with state-ofthe-art 4T pixels for comparison. The new pixels feature a pitch of 7.5 μm and a fill factor of 66%. A 0.4erms input-referred noise and a 185-μV/econversion gain are obtained. Compared with state-of-the-art pixels, also present onto the test chip, the rms noise is divided by more than 2 and the conversion gain is multiplied by 2.2.

A 533pW NEP 31×31 pixel THz image sensor based on in-pixel demodulation

A THz 31×31 pixel, 100 fps image sensor integrated in a 130 nm CMOS process is presented. Taking advantage of the possibility to modulate the active source that lights the scene, a significant improvement in sensitivity and NEP is achieved by shifting the modulated THz radiation, by means of an antenna/MOSFET, then filtering the signal band using an in-pixel 16-paths passive SC-filter combined with a CT Gm-C filter resulting in a high Q factor of 100. This THz imager features a measured NEP of 533 pW at 270 GHz and 732 pW at 600 GHz respectively, and a sensitive readout chain with an input referred noise of 0.2 μVRMS.

A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process

A sub-0.5e_rms^- temporal read noise VGA (640H×480V) CMOS image sensor has been integrated in a standard 0.18 μm 4PM CMOS process. The low noise performance is achieved exclusively through circuit optimization without any process refinements. The presented imager relies on a 4T pixel of 6.5 μm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. With a pixel bias of 1.5 μA the sensor chip features an input-referred noise histogram from 0.25 e_rms^- to a few e_rms^- peaking at 0.48 e_rms^-. The imager features a full well capacity of 6400 e^- and its frame rate can go up to 80 fps. It also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e^-/s. It is also shown that the implementation of the in-pixel n-well does not impact the quantum efficiency of the pinned photo-diode.

Recent trends in low-frequency noise reduction techniques for integrated circuits

This paper presents the two main circuit techniques, namely autozeroing (AZ) and chopper stabilization (CS), that are used to reduce the 1/f noise and offset in amplifiers typically used in sensor electronics interfaces. After recalling their main properties, it looks into recent trends in circuit noise reduction techniques. First, the correlated multiple sampling (CMS) technique is presented as a generalization of AZ and correlated double sampling (CDS). Introduced in CMOS image sensors (CIS), it combines noise averaging and canceling and allows to further reduce the 1/f noise, but, like AZ, it is also ultimately limited by the aliasing of the broadband white noise. Another technique combining noise canceling and CS in a transimpedance amplifier (TIA) for bio-sensors is presented. It allows to maintain a low input impedance required by the TIA, while reducing the noise of the main transimpedance stage. CS is then used to cancel the noise of the following stages.

Design optimization for low light CMOS image sensors readout chain

For a CIS readout chain based on 4T pixel, column amplification and CDS, we confirm that thermal noise can be reduced to be neglected compared to 1/f noise using parameters independent of the pixel design, namely column level gain, bandwidth control or correlated multiple sampling (CMS). Based on analytic noise calculation and simulation results using 180nm process, we show that CMS has no advantage over CDS for thermal noise reduction but offers slightly more 1/f noise reduction (about 20% less 1/f noise if high number of samples is used). 1/f and RTS noise originating from the in-pixel source follower transistor are reported to be the dominant noise sources in CIS readout chain. Based on analytic noise calculation, we demonstrate that, for a given CMOS process, the input referred 1/f noise is minimal for a unique pair of gate dimensions of the in-pixel source follower and we give its expression as a function of technological parameters.

A correlated multiple sampling passive switched capacitor circuit for low light CMOS image sensors

After a brief review of the principle of correlated multiple sampling (CMS) and its implementation techniques in CIS readout chains, a simple CMS passive circuit that (i) requires no additional active circuitry, (ii) has no impact on the output dynamic range and (iii) does not need multiple analog-to-digital conversions (faster) is presented. The proposed circuit uses n switched capacitors to perform a CMS on 2n samples. It is validated using transient noise simulations on a CIS readout chain based on a 4T pixel, designed with a 180nm CIS process. For a line readout time of 35 μs and a column amplifier bandwidth of 256 kHz, the proposed circuit reduces the input-referred noise as expected by an ideal CMS.

Noise Reduction Techniques and Scaling Effects towards Photon Counting CMOS Image Sensors

This paper presents an overview of the read noise in CMOS image sensors (CISs) based on four-transistors (4T) pixels, column-level amplification and correlated multiple sampling. Starting from the input-referred noise analytical formula, process level optimizations, device choices and circuit techniques at the pixel and column level of the readout chain are derived and discussed. The noise reduction techniques that can be implemented at the column and pixel level are verified by transient noise simulations, measurement and results from recently-published low noise CIS. We show how recently-reported process refinement, leading to the reduction of the sense node capacitance, can be combined with an optimal in-pixel source follower design to reach a sub-0.3erms- read noise at room temperature. This paper also discusses the impact of technology scaling on the CIS read noise. It shows how designers can take advantage of scaling and how the Metal-Oxide-Semiconductor (MOS) transistor gate leakage tunneling current appears as a challenging limitation. For this purpose, both simulation results of the gate leakage current and 1/f noise data reported from different foundries and technology nodes are used.

Comparison of two optimized readout chains for low light CIS

We compare the noise performance of two optimized readout chains that are based on 4T pixels and featuring the same bandwidth of 265kHz (enough to read 1Megapixel with 50frame/s). Both chains contain a 4T pixel, a column amplifier and a single slope analog-to-digital converter operating a CDS. In one case, the pixel operates in source follower configuration, and in common source configuration in the other case. Based on analytical noise calculation of both readout chains, an optimization methodology is presented. Analytical results are confirmed by transient simulations using 130nm process. A total input referred noise bellow 0.4 electrons RMS is reached for a simulated conversion gain of 160μV/e−. Both optimized readout chains show the same input referred 1/f noise. The common source based readout chain shows better performance for thermal noise and requires smaller silicon area. We discuss the possible drawbacks of the common source configuration and provide the reader with a comparative table between the two readout chains. The table contains several variants (column amplifier gain, in-pixel transistor sizes and type).

Noise Reduction in CIS Readout Chains

The readout noise analysis detailed in the previous chapter led to the derivation of the input-referred read noise for CIS readout chains based on in-pixel source follower and common source stage. For the 1 / f noise, the two configurations are equivalent but for the thermal noise, the common source stage may have a slight advantage.

Noise Sources and Mechanisms in CIS

The operation principles of the conventional low noise CIS presented in the previous Chapter can suffer from non-idealities, defects and random fluctuations at different levels corrupting the integrity of the signal.