Christian Enz

Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization

In linear ICs fabricated in a low-voltage CMOS technology, the reduction of the dynamic range due to the dc offset and low frequency noise of the amplifiers becomes increasingly significant. Also, the achievable amplifier gain is often quite low in such a technology, since cascoding may not be a practical circuit option due to the resulting reduction of the output signal swing. In this paper, some old and some new circuit techniques are described for the compensation of the amplifiers most important nonideal effects including the noise (mainly thermal and 1/f noise), the input-referred dc offset voltage as well as the finite gain resulting in a nonideal virtual ground at the input.

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQinv′ is controlled by the voltage differenceVP − Vch, whereVch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageVP is defined as the particular value ofVch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesVP − VS andVP − VD. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentID is derived and expressed as the difference between a forward componentIF and a reverse componentIR. Each of these is proportional to a function ofVP − VS, respectivelyVP − VD, through a specific currentIS. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

Minimum-energy broadcast in all-wireless networks: NP-completeness and distribution issues

In all-wireless networks a crucial problem is to minimize energy consumption, as in most cases the nodes are battery-operated. We focus on the problem of power-optimal broadcast, for which it is well known that the broadcast nature of the radio transmission can be exploited to optimize energy consumption. Several authors have conjectured that the problem of power-optimal broadcast is NP-complete. We provide here a formal proof, both for the general case and for the geometric one; in the former case, the network topology is represented by a generic graph with arbitrary weights, whereas in the latter a Euclidean distance is considered. We then describe a new heuristic, Embedded Wireless Multicast Advantage. We show that it compares well with other proposals and we explain how it can be distributed.

WiseNET: an ultralow-power wireless sensor network solution

A wireless sensor network consists of many energy-autonomous microsensors distributed throughout an area of interest. Each node monitors its local environment, locally processing and storing the collected data so that other nodes can use it. To optimize power consumption, the Swiss Center for Electronics and Microtechnology has developed WiseNET, an ultralow-power platform for the implementation of wireless sensor networks that achieves low-power operation through a careful codesign approach. The WiseNET platform uses a codesign approach that combines a dedicated duty-cycled radio with WiseMAC, a low-power media access control protocol, and a complex system-on-chip sensor node to exploit the intimate relationship between MAC-layer performance and radio transceiver parameters. The WiseNET solution consumes about 100 times less power than comparable solutions.

MOS transistor modeling for RF IC design

This paper presents the basis of the modeling of the MOS transistor for circuit simulation at RF. A physical equivalent circuit that can easily be implemented as a Spice subcircuit is first derived. The subcircuit includes a substrate network that accounts for the signal coupling occurring at HF from the drain to the source and the bulk. It is shown that the latter mainly affects the output admittance Y22. The bias and geometry dependence of the subcircuit components, leading to a scalable model, are then discussed with emphasis on the substrate resistances. Analytical expressions of the Y parameters are established and compared to measurements made on a 0.25-/spl mu/m CMOS process. The Y parameters and transit frequency simulated with this scalable model versus frequency, geometry, and bias are in good agreement with measured data. The nonquasi-static effects and their practical implementation in the Spice subcircuit are then briefly discussed. Finally, a new thermal noise model is introduced. The parameters used to characterize the noise at HF are then presented and the scalable model is favorably compared to measurements made on the same devices used for the S-parameter measurement.

A CMOS chopper amplifier

This paper presents a CMOS chopper amplifier realized with a 2nd order low-pass selective amplifier, using continuous-time filtering technique. The circuit has been integrated in a 3 ¿m p-well low-voltage CMOS technology. The chopper DC gain is 32 dB with 200 Hz bandwidth. The equivalent low-frequency input noise is 63 nV/¿Hz and free from 1/f noise. The input offset is typically 5 ¿V. The amplifier consumes only 34 ¿W and is therefore well suited for biomedical applications, like electrogram amplification.

Design of high-Q varactors for low-power wireless applications using a standard CMOS process

New applications such as wireless integrated network sensors (WINS) require radio-frequency transceivers consuming very little power compared to usual mainstream applications, while still working in the ultra-high-frequency range. For this kind of application, the LC-tank-based local oscillator remains a significant contributor to the overall receiver power consumption. This statement motivates the development of good on-chip varactors available in a standard process. This paper describes and compares the available solutions to realize high-Q, highly tunable varactors in a standard digital CMOS submicrometer process. On this basis, quality factors in excess of 100 at 1 GHz, for a tuning ratio reaching two, have been measured using a 0.5-/spl mu/m process.

An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver

A broad range of high-volume consumer applications require low-power battery-operated wireless microsystems and sensors. These systems should conciliate a sufficient battery lifetime with reduced dimensions, low cost, and versatility. Their design highlights the tradeoff between performance, lifetime, cost, and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V, for single battery cell operation). These considerations are illustrated by the design of a prototype receiver chip realized in a standard 0.5-/spl mu/m digital CMOS process with 0.6-V threshold voltage. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit operates at 1-V power supply in the 434-MHz European ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kb/s.

CMOS low-power analog circuit design

This chapter covers device and circuit aspects of low-power analog CMOS circuit design. The fundamental limits constraining the design of low-power circuits are first recalled with an emphasis on the implications of supply voltage reduction. Biasing MOS transistors at very low current provides new features but requires dedicated models valid in all regions of operation including weak, moderate and strong inversion. Low-current biasing also has a strong influence on noise and matching properties. All these issues are discussed, together with the particular aspects related to passive devices and parasitic effects. The design process has to be supported by efficient and accurate circuit simulation. To this end, the EKV compact MOST model for circuit simulation is presented. The use of the basic concepts such as pinch-off voltage, inversion factor and specific current are highlighted thanks to some very simple but fundamental circuits and to an effective use of the model. New design techniques that are appropriate for low-power and/or low-voltage circuits are presented with an emphasis on the analog floating point technique, the instantaneous companding principle, and their application to filters.

Poster abstract: wiseMAC, an ultra low power MAC protocol for the wiseNET wireless sensor network

WiseMAC is a medium access control protocol designed for the WiseNET™ wireless sensor network. It is based on CSMA and uses the preamble sampling technique to minimize the power consumed when listening to an idle medium. A unique feature of this protocol is to exploit the knowledge of the sampling schedule of its direct neighbors in order to use a wake-up preamble of minimized size. This scheme allows not only to reduce the transmit and the receive power consumption, but also brings a drastic reduction of the energy wasted due to overhearing. Backoff and medium reservation schemes have been selected to provide fairness and collision avoidance. WiseMAC requires no set-up signaling, no network-wide time synchronization and is adaptive to the traffic load. It provides an ultra-low average power consumption in low traffic conditions and a high energy efficiency in high traffic conditions.