F. Krummenacher

An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications

A fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented. All the large- and small-signal variables, namely the currents, the transconductances, the intrinsic capacitances, the non-quasi-static transadmittances and the thermal noise are continuous in all regions of operation, including weak inversion, moderate inversion, strong inversion, conduction and saturation. The same approach is used to derive all the equations of the model: the weak and strong inversion asymptotes are first derived, then the variables of interest are normalized and linked using an appropriate interpolation function. The model exploits the inherent symmetry of the device by referring all the voltages to the local substrate. It is shown that the inversion chargeQinv′ is controlled by the voltage differenceVP − Vch, whereVch is the channel voltage, defined as the difference between the quasi-Fermi potentials of the carriers. The pinch-off voltageVP is defined as the particular value ofVch such that the inversion charge is zero for a given gate voltage. It depends only on the gate voltage and can be interpreted as the equivalent effect of the gate voltage referred to the channel. The various modes of operation of the transistor are then presented in terms of voltagesVP − VS andVP − VD. Using the charge sheet model with the assumption of constant doping in the channel, the drain currentID is derived and expressed as the difference between a forward componentIF and a reverse componentIR. Each of these is proportional to a function ofVP − VS, respectivelyVP − VD, through a specific currentIS. This function is exponential in weak inversion and quadratic in strong inversion. The current in the moderate inversion region is then modelled by using an appropriate interpolation function resulting in a continuous expression valid from weak to strong inversion. A quasi-static small-signal model including the transconductances and the intrinsic capacitances is obtained from an accurate evaluation of the total charges stored on the gate and in the channel. The transconductances and the intrinsic capacitances are modelled in moderate inversion using the same interpolation function and without any additional parameters. This small-signal model is then extended to higher frequencies by replacing the transconductances by first order transadmittances obtained from a non-quasi-static calculation. All these transadmittances have the same characteristic time constant which depends on the bias condition in a continuous manner. To complete the model, a general expression for the thermal noise valid in all regions of operation is derived. This model has been successfully implemented in several computer simulation programs and has only 9 physical parameters, 3 fine tuning fitting coefficients and 2 additional temperature parameters.

A 4-MHz CMOS continuous-time filter with on-chip automatic tuning

This paper presents a 3rd order low-pass continuous-time filter with 4 MHz cut-off frequency, integrated in a 3 μm CMOS process. The design approach is based on the direct simulation of a doubly-terminated LC ladder using capacitors and fully-balanced, current-controlled transconductance amplifiers with extended linear range. PLL techniques, involving a 8.5 MHz controlled oscillator that matches a specific part of the filter, are used to realize on-chip automatic tuning. The complete circuit features 71 dB dynamic range and consumes only 16 mW from a single 5 V supply.

Random error effects in matched MOS capacitors and current sources

Explicit formulas are derived using statistical methods for the random errors affecting capacitance and current ratios in MOS integrated circuits. They give the dependence of each error source on the physical dimensions, the standard deviations of the fabrication parameters, the bias conditions, etc. Experimental results, obtained for both matched capacitors and matched current sources using a 3.5-/spl mu/m NMOS technology, confirmed the theoretical predictions. Random effects represent the ultimate limitation on the achievable accuracy of switched-capacitor filters, D/A converters, and other MOS analog integrated circuits. The results indicate that a 9-bit matching accuracy can be obtained for capacitors and an 8-bit accuracy for MOS current sources without difficulty if the systematic error sources are reduced using proper design and layout techniques.

A CMOS chopper amplifier

This paper presents a CMOS chopper amplifier realized with a 2nd order low-pass selective amplifier, using continuous-time filtering technique. The circuit has been integrated in a 3 ¿m p-well low-voltage CMOS technology. The chopper DC gain is 32 dB with 200 Hz bandwidth. The equivalent low-frequency input noise is 63 nV/¿Hz and free from 1/f noise. The input offset is typically 5 ¿V. The amplifier consumes only 34 ¿W and is therefore well suited for biomedical applications, like electrogram amplification.

A model for /spl mu/-power rectifier analysis and design

This paper proposes a linear two-port model for an N-stage modified-Greinacher full-wave rectifier. It predicts the overall conversion efficiency at low power levels where the diodes are operating near their threshold voltage. The output electrical behavior of the rectifier is calculated as a function of the received power and the antenna parameters. Moreover, the two-port parameter values are computed for particular input voltages and output currents for the complete N-stage rectifier circuit using only the measured I-V and C-V characteristics of a single diode. To validate the model a three-stage modified-Greinacher full-wave rectifier was realized in an silicon-on-sapphire (SOS) CMOS 0.5-/spl mu/m technology. The measurements are in excellent agreement with the values calculated using the presented model.

Pixel detectors with local intelligence: an IC designer point of view

Abstract Scaling laws for the analog front end and related problems are discussed for detectors in the range from microstrips to pixel detectors. Design strategies for fast- and low-power building blocks (charge-sensitive preamplifier, shaper, discriminator and analog storage) are looked into. Merging of functions for minimal transistor counts, local analog storage versus digital-only output (trade-offs and limitations) and precision of and matching between readout elements are also discussed.

Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model

Abstract In this paper, the implications of inversion charge linearization in compact MOS transistor modeling are discussed. The charge-sheet model provides the basic relation among inversion charge and applied potentials, via the implicit surface potential. A rigorous derivation of simpler relations among inversion charge and applied external potentials is provided, using the technique of inversion charge linearization versus surface potential. The new concept of the pinch-off surface potential and a new definition of the inversion charge linearization factor are introduced. In particular, we show that the EKV charge-based model can be considered as an approximation to the more general approach presented here. An improvement to the EKV charge-based model is proposed in the form of a more accurate charge–voltage relationship. This model is analyzed in detail and shows an excellent agreement with the charge sheet model. The normalization of voltages, current and charges, as motivated by the inversion charge linearization, results in a major simplification in compact modeling in static as well as non-quasi-static derivations.

LHC1: A semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 × 16 readout cells of 50 μm × 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼ 100 e− rms. The lowest threshold setting is close to 2000 e− and non-uniformity has been measured to be better than 450 e− rms at 5000 e− threshold. A timewalk of < 10 ns and a precision of < 6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization.

Silicon Resonator Based 3.2

This paper presents an ultra-low power generic compensation scheme that is used to implement a real time clock based on an AlN-driven 1 MHz uncompensated silicon resonator achieving 3.2 μW power dissipation at 1 V and ±10 ppm frequency accuracy over a 0-50°C temperature range. It relies on the combination of fractional division and frequency interpolation for coarse and fine tuning respectively. By proper calibration and application of temperature dependent corrections, any frequency below that of the uncompensated resonator can be generated yielding programmability, resonator fabrication tolerances and temperature drift compensation without requiring a PLL. To minimize the IC area, a dual oscillator temperature measurement concept based on a ring oscillator/resistor thermal sensor was implemented yielding a resolution of 0.04°C. The IC was fabricated on a 0.18 μm 1P6M CMOS technology.

\mu

Abstract A second version of the Omega pixel readout chip has been developed in order to make it compatible with large area coverage. Specific features of the new chip include a reset which can be applied immediately following a “false” trigger, an improved minimum strobe time of ∼ 100 ns, a readout clock rate of ∼ 20 MHz and tri-state buffers on the output data lines. The excellent performance figures of the first chip for noise (100 e rms without detector and 170 e rms with detector) and power consumption (30 μW/pixel) have been maintained. We demonstrate how with solder bump-bonding we can create hybrid “ladders” which hermetically cover an area of ∼ 5 mm × 50 mm. Potential problems of electrical matching and yield have been addressed and procedures are in place for selecting only “good” readout chips for mounting.