Atanu Kundu

Comparisons between Dual and Tri Material Gate on a 32 nm Double Gate MOSFET

The paper reports a comparative analysis between the dual material gate double gate (DMG-DG) nMOSFET and the tri material gate double gate (TMG-DG) nMOSFET in terms of their analog and RF performance. Three different devices having the DMG-DG structure have been considered. Each of the devices have different higher workfunction material gate length (L1) to lower workfunction material gate length (L2) ratio (L1:L2). Along with the three devices, the performance of the TMG-DG nMOSFET is compared. The analog parameters considered for the comparison are the drain current (Ids), the transconductance (gm), the transconductance generation factor (gm/Ids) and the intrinsic gain (gmRo). The drain induced barrier lowering (DIBL) of the devices is compared. The RF analysis is performed using the non quasi static (NQS) approach. We consider the intrinsic gate to source capacitances (Cgs), the intrinsic gate to drain capacitance (Cgd), the intrinsic gate to source resistances (Rgs), the intrinsic gate to drain resistance (Rgd), the transport delay (τm), the unity current gain cut-off frequency (fT) and the max frequency of oscillation (fmax) for the RF comparisons. A single stage amplifier is also implemented using the devices for a circuit comparison.

RF parameter extraction of underlap DG MOSFETs: a look up table based approach

In this study, a look up table (LUT) is developed to extract the intrinsic RF parameters of underlap DG MOSFET (UDG-MOSFET) including the non-quasi-static (NQS) effect. The LUT-based approach proposed; can accurately extract complex RF parameters of UDG-MOSFET under different bias conditions, necessary for RF circuit simulations by an interpolation algorithm. The RF parameters including intrinsic gate to drain capacitance (C gd), gate to source capacitance (C gs), gate to drain resistance (R gd), gate to source resistance (R gs), gate to source transconductance (gm ), drain to source transconductance (g ds), transport delay (τm ), capacitance because of DIBL (C sdx) and inductance because of transport delay (L sd), cut-off frequency (f T) and maximum frequency of oscillation (f max) are extracted using LUT approach. Parameters extracted using LUT are compared with simulated data, considering the NQS effect, and are found in good agreement. For RF circuit applications a low-noise amplifier is designed, with the UDG-MOSFET, operating at a tuned frequency of 10 GHz.

RF parameter extraction of Bulk FinFET: A non quasi static approach

In this paper, we present a simple and accurate method to extract the parasitic as well as the intrinsic components of a Bulk FinFET device. Based on the Y- parameter data obtained from the 3-dimensional device simulator Sentaurus TCAD, the parasitic components are de-embedded and an accurate modeling based on the equivalent small signal circuit is presented to extract the intrinsic parameters. The non-quasi static effect is included and so the model predicts the Y parameter values accurately at high frequencies.

Analog/RF performance comparison of underlap gate stack DG NMOSFETs in sub 65nm regime

This paper consists of comparative study of U-DG-GS-NMOSFET for different channel lengths(Lch). Channel length below 100 nm leads to Short Channel Effects (SCEs). Gate Induced Drain Leakage (GIDL) and Drain Induced Barrrier Lowering are the major problem for any short channel device. Gate Stack arrangement is used to reduce GIDL and source-drain underlap regions are used to minimize the effects of DIBL. The length of the underlap (Lu) region is optimized for 32nm channel length. With the optimized underlap length, the device performance for different channel lengths such as 32nm, 45nm and 65nm have been studied. The device performance which have been studied are transfer characteristics, drain characteristics, transconductance (gm), transconductance generation factor (gm/Ids), output resistance(Ro), intrinsic gain(gmRo), total gate capacitance (Cgg), cut-off frequency (fT), maximum frequency of oscillation(fmax).

Symmetric/asymmetric underlap DG-MOSFET: A study of analog/RF performance using non-quasi static approach

In this paper, analog/RF performance of symmetric and asymmetric Double Gate MOSFETs (DGMOS), with an optimized underlap length, have been compared and analyzed. High k material (HfO<inf>2</inf>) with SiO<inf>2</inf> padding is used to reduce gate tunneling and scattering of electrons respectively. The on current (I<inf>ON</inf>), transconductance (g<inf>m</inf>), transconductance generation factor (g<inf>m</inf>/I<inf>D</inf>), cut-off frequency (f<inf>T</inf>) and maximum frequency of oscillation (f<inf>max</inf>) have been studied. This has been observed from the data obtained from 2D numerical simulator Sentaurus TCAD and RF analysis is performed using non-quasi static approach (NQS).

Effect of channel engineering on analog/RF performance of underlapped gatestack DG-MOSFET in Sub-20nm regime

In this paper the effects of channel engineering on device performance in Symmetric Underlap Gatestack DoubleGate NMOSFET has been thoroughly analyzed. A device with undoped channel has been compared with two devices having doping in source and drain side respectively. It has been observed that the graded channel with heavily doped source side offers significant improvement in analog performance such as on-current, transconductance, intrinsic gain and in RF performance like cut-off frequency, maximum frequency of oscillation. The performance of a single stage amplifier circuit is also been enhanced using the device as the driver MOSFET and the AC gain analysis is also been done in this work.

UDGMOSFET based analog circuit blocks in cadence virtuoso

In the present study, a look up table (LUT) based approach is used to extract device characteristics of an SOI based UDGMOSFET built in TCAD and imported to Cadence Virtuoso to implement analog circuit blocks. In particular, this study utilizes the custom 14nm UDGMOSFET to build a simple CMOS inverter, a single ended voltage amplifier and a Schmitt Trigger circuit. The circuits are simulated in Cadence Virtuoso environment and the performance is compared with results obtained from similar simulations in TCAD, the motivation being to prove that analyses can be conducted in Cadence with comparable efficiency as TCAD but in significantly shorter duration of time.