Arka Dutta

Subthreshold Analog/RF Performance Enhancement of Underlap DG FETs With High- K Spacer for Low Power Applications

This paper presents a systematic study of the subthreshold analog/RF performance for underlap double gate (UDG) NMOSFETs using high dielectric constant (k) spacers. The conventional UDG-NMOSFETs offer reduced short-channel effects along with improved subthreshold analog/RF performance at a cost of higher distributed channel resistance and low on current. In this paper, we show that these drawbacks can be alleviated effectively by using high-k spacers without any severe degradation in the subthreshold analog/RF performance. In order to show the improvement in the device performance, we have studied the effect of high-k spacers on different subthreshold analog figures of merit such as the transconductance, transconductance generation factor, output resistance, and the intrinsic gain for different values of k . Moreover, we have analyzed the RF performance as a function of intrinsic capacitance and resistance, transport delay, inductance, cutoff frequency, and the maximum oscillation frequency. In order to assess the gain bandwidth (GBW) product, the circuit implementation of the UDG-NMOSFETs with different high-k spacers was performed on a common source amplifier. Our results show an improvement in the GBW of about 38% for the devices with high- k spacers compared to its low- k counterpart.

Analysis of High-

In this paper, asymmetric underlap double-gate (AUDG) MOSFET is studied to analyze the influence of high-k spacer on the intrinsic device parameters. The AUDG-MOSFET architecture offers better device performance, particularly, drain-induced barrier lowering in contrast to the conventional double-gate (DG)-MOSFET. However, the ON current and the distributed resistances for the device increase considerably. The analysis of the device presented here shows that the detrimental effects of the device can be effectively eliminated using high-k spacers. To evaluate the device performance and to study the improvement associated with the use of high-k spacers, different intrinsic parameters are analyzed. These parameters include transconductance (g_m), transconductance generation factor (g_m/I_d), intrinsic gain (g_mr_o), intrinsic capacitance (C_gd, C_gs), resistance (R_gd, R_gs), transport delay (τ_m), inductance (L_sd), cutoff frequency (f_T), and the maximum frequency of oscillation (f_max), gain bandwidth product, and inverter delay.

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Implementation of digital controllers in embedded environment suffers from the inherent problems associated with analog-digital signals interfacing in hard real-time, therefore, the control algorithms are invariantly subjected to approximations. This paper presents a novel technique for implementation of an efficient FPGA based digital Proportional-Integral-Derivative (PID) controller for the motion control of a permanent magnet DC motor. The implementation technique circumnavigates the problem of interfacing analog and digital systems in real-time. The controller is used in a speed control loop. The hardware implementation has been done on a Xilinx Spartan 3 FPGA chip. A novel technique has been adopted for the generation of the control input as a PWM signal for controlling the motor driver circuit and decoding the optical encoder data for using it for the speed feedback in the PID control loop. The VHDL algorithm for the proposed implementation has also been presented in this paper. A comparison of the experimental results with the Matlab® based simulation shows the effectiveness of the proposed method.

Spacer Asymmetric Underlap DG-MOSFET for SOC Application

Abstract The underlap double gate MOSFET (UDG-MOSFET) has been well established as a potential candidate for the RF applications. However, before implementation the various process related variations are required to be addressed for the better dependability. In this paper, the effect of process dependent parameter variations on the RF performance of the UDG-MOSFET is analyzed. The process dependent parameters considered are the oxide and the body thicknesses. The RF performance of UDG-MOSFET is analyzed as a function of RF figure of merits (FOMs), intrinsic capacitance (Cgs, Cgd), intrinsic resistance (Rgs, Rgd), transport delay (τm), inductance (Lsd) and analog FOMs transconductance (gm), transconductance generation factor (gm/Id), output resistance (Ro) and intrinsic gain (gmRo). The analysis is performed using the non-quasi static (NQS) small signal model of the UDG-MOSFET.

An FPGA based implementation of a flexible digital PID controller for a motion control system

Floating-Point addition imposes a great challenge during implementation of complex algorithm in hard real-time due to the enormous computational burden associated with repeated calculations with high precision numbers. Moreover, at the hardware level, any basic addition or subtraction circuit has to incorporate the alignment of the significands. This paper presents a novel technique to implement a double precision IEEE floating-point adder that can complete the operation within two clock cycles. The proposed technique has exhibited improvement in the latency and also in the operational chip area management. The proposed double precision IEEE floating-point adder has been implemented with XC2V6000 and XC3S1500 Xilinx© FPGA devices.

Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs

Abstract In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.

FPGA based implementation of a double precision IEEE floating-point adder

In this paper, the harmonic distortion (HD) in the underlap double-gate MOSFETs (UDG-MOSFETs) with high- k spacers is analyzed. The HD occurs due to the nonlinearity in the device performance and therefore, a detailed analysis of the HD as a function of spacer dielectric constant (k) is critical to ensure device reliability for RF performance. In this paper, the analysis is performed for the primary components, the second-order distortion (HD2), and the third-order distortion (HD3) along with the total HD. The parameters analyzed for the HD study of the UDG-MOSFETs with high- k spacers are the drain current, the transconductance, and the transconductance generation factor. The results of the analysis suggest a reduction in the distortion phenomenon for the high- k spacer devices, thereby ensuring reliability of these devices for RF applications. Also, a detailed analysis of HD2 and HD3 as a function of k of the high- k spacers are performed using UDG-MOSFETs in cascode and differential amplifier circuits.

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

This paper presents a systematic study of the effect of source/drain (S/D) implant lateral straggle on the RF performance of the symmetric and asymmetric underlap double gate (UDG) MOSFET devices. The length of the underlap regions (Lun) on each side of the gate is a critical technology parameter in determining the performance of UDG-MOSFETs. However, the value of Lun is susceptible to variation due to S/D implant lateral diffusion. Therefore, it is critical to investigate the impact of S/D implant lateral straggle on the performance of UDG-MOSFETs. This paper shows that the improvement in the RF performance of the UDG-MOSFETs over the conventional DG-MOSFETs can be achieved by optimizing the S/D lateral straggle of the asymmetric UDG-MOSFETs. The RF performance study includes intrinsic capacitances and resistances, transport delay, inductance, and the cut-off frequency.

Analysis of Harmonic Distortion in UDG-MOSFETs

Abstract In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (t oxh ) and channel length (L g ) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in t oxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.

Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs

This paper presents the formulation of a novel block-backstepping based control algorithm to address the global stabilization problem of a flat underactuated inertia wheel system. The ideas behind the method are as follows. At first, state model of the inertia wheel system has been converted into block-strict feedback form. Then the control Lyapunov function has been designed for each cascaded dynamic block to derive the expression of the control input for the overall nonlinear system. The overall asymptotic stability of the inertia wheel system has been analyzed using Lyapunov Stability Criteria. Finally, the effectiveness of the proposed control algorithm has been verified in the simulation environment.