Atsuhiko Ikeuchi

Lithography oriented DfM for 65 nm and beyond

As Technology node is advancing, we are forced to use relatively low resolution lithography tool. And these situation results in degradation of pattern fidelity. hot spot, lithographic margin-less spot, appears frequently by conventional design rule methodology. We propose two design rule methodology to manage hot spot appearances in the stage of physical pattern determination. One is restricted design rule, under which pattern variation is very limited, so hot spot generation can be fully controlled. Second is complex design rule combined with lithography compliance check (LCC) and hot spot fixing (HSF). Design rule, by itself, has a limited ability to reduce hot spot generation. To compensate the limited ability, both LCC including optical proximity correction and process simulation for detecting hot spots and HSF for fixing the detected hot spots are required. Implementing those methodology into design environment, hot spot management can be done by early stage of physical pattern determination. Also newly developed tool is introduced to help designers easily fixing hot spots. By using this tool, the system of automatic LCC and HSF has been constructed. hot spots-less physical patterns through this system can be easily obtained and turn-back from manufacture to design can be avoided.

A circuit comparison system with rule-based functional isomorphism checking

A circuit comparison system is described which compares two networks and points out inconsistencies. A novel approach is used to handle functionally isomorphic circuits which most conventional programs can not handle. Three techniques are included: network reduction, graph isomorphism-based comparison, and rule-based functional isomorphism checking for inconsistencies. The system is efficient even for large networks and can eliminate false errors in flexible manner.<<ETX>>

Efficient hybrid optical proximity correction method based on the flow of design for manufacturability (DFM)

Design and optical proximity correction (OPC) flow with hybrid OPC and manufacturability check (MC) tool was found to be effective for making robust pattern formation without any hot spots within feasible lead time under the low-k1 lithography condition. MC at design stage is essential for cleaning up hot spots in three ways; the refinement of design rule, the guideline for repairing hot spots for designers and the refinement of OPC deck. Hybrid OPC and MC tools with library- and model-based modules are available for reducing lead time by taking advantage of library system. Due to the design and OPC flow with the library-based OPC and MC tool, total lead time can be reduced to 55% of that in the case of conventional flow with MC. Assuming that a refined mask is ordered due to issue of hot spots without MC, the total lead time in the new flow can be reduced to 11% of that in the case of conventional technology.

Validation of process cost effective layout refinement utilizing design intent

Continuous shrinkage of design rule (DR) in ultra-large-scale integrated circuit (ULSI) devices brings about greater difficulty in the manufacturing process. The keys to meeting small process margin are adequate extraction of critical dimension (CD) tolerance for each object and budgeting the tolerance for each process step. Furthermore, to extract adequate tolerance, design intent in terms of electrical behavior should be carefully considered. Electrical behavior is carefully verified in design stages using various electronic design automation (EDA) tools. However, once the design data is converted to layout data and signed off, most of the design intent is abandoned and unrecognized in the process stage. Thus, instead of essential tolerance assignment according to layout-related design intent, uniform and redundant tolerance is used, and so excess tolerance is assigned for some layouts. To solve the problem described above, a tolerance-based manufacturing system utilizing flexible layout-dependent speculation derived from design intent has been discussed. In this paper, test flow utilizing design intent is developed. In the flow, electrical small-margin spots are extracted, verified with customized criteria according to the tolerance derived from design intent, and fixed in the process. The proposed flow is examined and validated for the application to 40nm node test chip.