Suigen Kyoh

Automated hot-spot fixing system applied for metal layers of 65 nm logic devices

Hot spot clearance using process simulation is indispensable under low-k1 lithography process for logic devices of 65 nm and below. Hot spots such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Appropriate calibration of design rule (DR), mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of design at hot spot will be effective, but it takes too much time to determine how to modify layout to be consistent with DR, MDP/OPC rule, and the process often needs to be iterative. Therefore, there is a need for an automated hot spot fixing system is capable of fixing design layout so as to avoid fatal hot spot occurrence, with sufficient process margin and short turn around time (TAT). We developed an automated hot-spot fixing system, Hot Spot Fixer (HSF). The basic system flow in the developed system is as follows; Design data is processed with the conventional mask data preparation process. Then, process simulation is performed to extract hot spots. The hot spots are categorized by lithography error mode, critical level, and surrounding context. An intelligent hot-spot modification instructor, taking the surrounding situation into consideration, generates modification guide for the every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. If necessary, several modification candidates are indicated and the user can choose the most adequate one from them. The design modification process is verified from every aspect, using Design Rule Checker (DRC) and process simulation. The modified design data, with reduced potential hot spot compared with pre-modification design, is processed under the conventional mask data preparation process again, and then makes mask data, which will reduce the number of potential hot spot. We applied the HSF system to metal layer of logic devices of 65 nm and then the hot spots are almost diminished throughout a full chip within twelve hours. Thus HSF feasibility has been proved for metal layers in 65 nm node and below with full chip data volume.

Lithography oriented DfM for 65 nm and beyond

As Technology node is advancing, we are forced to use relatively low resolution lithography tool. And these situation results in degradation of pattern fidelity. hot spot, lithographic margin-less spot, appears frequently by conventional design rule methodology. We propose two design rule methodology to manage hot spot appearances in the stage of physical pattern determination. One is restricted design rule, under which pattern variation is very limited, so hot spot generation can be fully controlled. Second is complex design rule combined with lithography compliance check (LCC) and hot spot fixing (HSF). Design rule, by itself, has a limited ability to reduce hot spot generation. To compensate the limited ability, both LCC including optical proximity correction and process simulation for detecting hot spots and HSF for fixing the detected hot spots are required. Implementing those methodology into design environment, hot spot management can be done by early stage of physical pattern determination. Also newly developed tool is introduced to help designers easily fixing hot spots. By using this tool, the system of automatic LCC and HSF has been constructed. hot spots-less physical patterns through this system can be easily obtained and turn-back from manufacture to design can be avoided.

Process window aware layout optimization using hot spot fixing system

The feasibility of Hot Spot Fixing (HSF) system in DfM flow is studied and reported. Hot spot fixing using process simulation is indispensable under low-k1 lithography process for logic devices with advanced design rule (DR). Hot spot such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Proper calibration of DR, mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with most careful calibration of every process, unexpected potential hot spots are occasionally left in the design layout 1-2. OPC optimization is useful for maximizing common process margin, but it cannot expand individual patterns process margin without modification of design layout. So, at an early design stage, hot spot extraction using lithography compliance check (LCC) and manual modification of design at hot spots will be a simple and useful method. The problem is that, it is difficult to determine how to modify layout in order to be consistent with DR, MDP/OPC rule. For proper layout modification, intimate knowledge of the entire process would be necessary, and moreover, the modification work often tends to be iterative, and thus time-consuming. Therefore, using our automated HSF system in the cell design stage and also the chip design stage is helpful for fixing design layout while avoiding fatal hot spot occurrence, with enough process margin and also with short turnaround time (TAT) 3-4. The basic system flow in the developed system is as follows; LCC extracts potential hot spots, and the hot spots are categorized by lithography error mode, grade, and surrounding context. And then, hot spot modification instructor, taking the surrounding situation into consideration, generates modification guide for every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. The design modification process is verified with design-rule checker (DRC) and process simulation to confirm hot spot elimination without side effect. In this work, HSF is implemented in the design flow for various logic devices of 65 nm node. We extend modification target layers to multiple critical layers, including active area, poly, local metal wire and intermediate metal wire. The feasibility of the provided HSF system has been studied by applying it to around one hundred data of various sizes with respect to pattern fixing rate and turn around time (TAT). Moreover, process margin expansion including depth of focus (DOF) and exposure latitude (EL), in small layout was verified using process simulation and also by experimental results, namely, scanning electron microscope (SEM) images of focus exposure matrix. The detailed results are shown in the paper.

Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices

Hot-spot clearance using process simulation is indispensable for low-k 1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.

Patterning strategy and performance of 1.3NA tool for 32nm node lithography

We have designed the lithography process for 32nm node logic devices under the 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for contact hole pattern, respectively. The isolated feature needs SRAF to pull up the DOF margin. High density SRAM cell with 0.15um2 area is clearly resolved across exposure and focus window. The 1.3NA scanner has sufficient focus and overlay stability. There is no immersion induced defects.

Accurate model base verification scheme to eliminate hotspots and manage warmspots

Lithography compliance check (LCC), which is verification of layouts using lithography simulation, is an essential step under the current low k1 lithography condition. However a conventional LCC scheme does not consider process proximity effect (PPE) differences among several manufacturing tools, especially for exposure tools. In this paper two concepts are proposed. One is PPE monitoring and matching using warmspots. The warmspots are patterns that have small process window. They are sensitive to difference of illumination conditions and are basically 2-dimensional patterns. The other is LCC using multiple simulation models that represent each PPE on exposure tools. All layouts are verified by these models and the layouts are fixed if hotspots (catastrophic failure on wafer) are found. This verification step is repeated until all hotspots are eliminated from the layouts. Based on these concepts, robust cell layouts that have no hotspot under the several PPE conditions are created.

Systematic yield estimation method applying lithography simulation

In this paper, we propose the novel method quantifying impacts of lithography hot spots to chip yield with lithography simulation. Our method consists of three steps. Firstly, lithography simulation is done under several conditions including process variations, exposure dose and focus, for example. Hot spots are recognized through the results of simulations and those critical dimensions (CD) are derived. Secondly, a failure rate is calculated under a process parameter at each hot spot, respectively. Assuming the distribution of wafer CD from simulated CD, a differential failure rate on a process parameter is calculated with integrating the probability that wafer CD is less than a lower limit. Also probability that process condition is equal to the process parameter is defined from a distribution of process parameter. Finally, individual failure rate of the hot spot is calculated by summing the products of the differential failure rate and the probabilities of process parameter. Systematic yield is calculating with multiplying the differences of the individual failure rate from unity, providing that all hot spots are fully individual. An advantage of this method is that the defect probability of hot spot is calculated independently from each other and systematic yield can be easily estimated regardless of layout size, from primitive cell to full chip.

Study of practical TAT reduction approaches for EUV flare correction

We introduce techniques of flare compensation for Extreme Ultraviolet Lithography that can reduce the calculation time of a flare map and flare correction. In the first approach, the range of a flare point spread function is divided into several regions and the size of meshes for the flare map in each region is selected. In the second approach, the size of the mask pattern is controlled by referring to the flare map in the mask-making process. In the third approach, dosage of each point in a mask corresponding to the flare map is modulated when transferring the mask pattern onto the resist. Use of these approaches in the proper combination is effective for TAT reduction and accuracy of the flare compensation.

Process liability evaluation for beyond 22nm node using EUVL

Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22- nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer process for device manufacture at the 22-nm node and beyond.

Evaluation of phase and transmittance error on deep-UV halftone phase-shift mask

The effect of phase shift and transmittance fluctuation in a mask plate have been studied. The differences of these optical properties of halftone phase shift masks result in critical dimension(CD) error on a wafer so that these fluctuation in a plate reduce the process window across the exposure field. In considering CD error budget, such factors as phase shift and transmittance has to be taken into account. To estimate this budget, a set of test masks were fabricated, in which phase shift and transmittance are varied, and the exposures using these masks under the same conditions were performed.