Atsuko Iida

The development of repairable Au-Al solid phase diffusion flip-chip bonding

The authors have developed a new repairable chip-on-glass (COG) bonding technique for liquid crystal display (LCD) panels. Gold (Au) bumps on an LSI chip were bonded directly to aluminum (Al) electrodes on a glass substrate by formation of Al-Au intermetallic compounds in the diffusion layer. The developed repairable bonding technique consists a of two-level bonding process. First, the chip was bonded at 250/spl deg/C. Partial interconnection could be obtained at the local contact portions between the Au bump and the Al electrode. If the electrical connection failed, the bonded chip was removed. There was a distribution of the area formed Al-Au intermetallic compounds at local contact portions for 250/spl deg/C bonding. Some areas formed Al-Au intermetallic compounds of the Al electrode were sometimes removed with the chip removal, and an underlying metal layer was locally exposed at the remained surface. Then, a new chip was bonded on the same Al electrodes under the same conditions at 250/spl deg/C. After obtaining the electrical connection, the second bonding was done at 350/spl deg/C. An AlAu4 intermetallic formation was obtained by this bonding in the diffusion layer. Reliability tests of second bonded samples were carried out and the contact resistance between the Au bumps and the Al electrodes was measured by the four-probe resistance measurement. In the case that the exposed area ratio of the underlying metal layer was less than 30% of bonding area for each Al electrode, the stable electrical connection has been kept for a high temperature storage test and a thermal shock test. It was confirmed that a stable electrical connection had been obtained by the proposed repairable bonding process.

A wafer-level heterogeneous technology integration for flexible pseudo-SoC

The MEMS-LSI integration technologies that have been reported are mainly implemented for monolithic integrated System on Chip (SoC) by applying the advantages of process compatibility between MEMS and CMOS LSI [1]. However, it has been impossible to integrate them in the case that MEMS and standard CMOS processes are incompatible. Furthermore, many MEMS-LSI integration technologies applying System in Package (SiP) technology with the interposer substrate to realize electronics devices have been reported. However, using SiP technology, it has not been possible to achieve high integration density comparable to that of monolithic integrated SoC because the interposer substrate occupies a large area in SiP. Accordingly, development of an advanced MEMS-LSI integration technology to realizing highly integrated SoC incorporating MEMS devices is required [2].

An investigation of stable bonding for Au–Al solid phase diffusion bonding techniques

By using a chip that has Au bumps and a substrate that has only a varying Al film thickness, initial bonding strength is made constant in Au–Al solid-phase diffusion bonding. On the other hand, by changing the Au–Al intermetallic compound formed during bonding, a relationship is obtained between the formed intermetallic compound and bonding reliability. Samples obtained when installing ICs under the same conditions on substrates with Al film thicknesses of 350 nm and 1000 nm were left for 1000 hours at 125 °C and the bonding strength and connection resistance were measured. Immediately after bonding, there was no meaningful difference between them. However, after 1000 hours, reduced bonding strength and increased connection resistance were observed in the sample whose Al film thickness was 1000 nm whereas a stable connection was obtained in the sample whose Al film thickness was 350 nm. The difference in reliability in a high-temperature environment results from differences in the Au–Al intermetallic compounds formed at the time of bonding and by the existence of unreacted Al. In the sample whose Al film thickness was 350 nm, there was no Al at the junction at the time of bonding, so that the final product was predominantly Au4Al. On the other hand, in the sample whose Al film thickness was 1000 nm, Al existed at the junction, so that several Au–Al intermetallic compounds were formed which subsequently degrade by diffusion reactions at high temperature.

A wafer-level system integration technology for flexible pseudo-SOC incorporates MEMS-CMOS heterogeneous devices

A flexible pseudo-SoC which integrates electrostaticMEMS and its driver CMOS-LSI for mobile electronics device applications has been developed. From the experiments, the pseudo-SoC process has succeeded to form a fine-pitch on-chip global layer on the MEMS and CMOS-LSI embedded in the epoxy resin and to realize total thickness of 100µm. This paper reports the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC within the results of a highly-integrated flexible pseudo-SoC incorporating electrostatic MEMS and its driver CMOS-LSI for mobile electronics applications.

Linear CMOS power amplifiers employing a novel layout configuration for improved stability and long-term reliability

This paper presents a design and characterization of linear CMOS power amplifiers employing a new layout configuration of transistors, assuming that both unstable operation known as memory effects and degradation of power transistors are caused by hot carrier effects through thermal energy accumulation and magnified impact ionization at the pinch-off channels by acoustic phonon. The new layout concept of the power transistors has been applied in a single-chip power amplifier circuit in class AB operation using 0.13 µm standard CMOS process. High-power durability tests have revealed that the transistors of the new type are free from significant degradation even in long-term continuous operations.