Atsushi Ike
Fujitsu
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Publication
Featured researches published by Atsushi Ike.
design, automation, and test in europe | 2012
David Thach; Yutaka Tamiya; Shinya Kuwamura; Atsushi Ike
In this paper, we propose a cycle estimation methodology for fast instruction-level CPU emulators. This methodology suggests achieving accurate software performance estimation at high emulation speed by utilizing a two-phase pipeline scheduling process: a static pipeline scheduling phase performed off-line before runtime, followed by an accuracy refinement phase performed at runtime. The first phase delivers a pre-estimated CPU cycle count while limiting impact on the emulation speed. The second phase refines the pre-estimated cycle count to provide further accuracy. We implemented this methodology on QEMU and compared cycle counts with a physical ARM CPU. Our results show the efficiency of the tradeoffs between emulation speed and cycle accuracy: cycle simulation error averages 10% while the emulation latency is 3.37 times that of original QEMU.
international workshop on machine learning for signal processing | 2016
Koichi Shirahata; Yasumoto Tomita; Atsushi Ike
Training deep neural networks requires a large amount of memory, making very deep neural networks difficult to fit on accelerator memories. In order to overcome this limitation, we present a method to reduce the amount of memory for training a deep neural network. The method enables to suppress memory increase during the backward pass, by reusing the memory regions allocated for the forward pass. Experimental results exhibit our method reduced the occupied memory size in training by 44.7% on VGGNet with no accuracy affection. Our method also enabled training speedup by increasing the mini batch size up to double.
symposium on vlsi circuits | 2016
Takashi Shimizu; Yasumoto Tomita; Hidetoshi Matsumura; Masahiko Sugimura; Hironobu Yamasaki; David Thach; Takashi Miyoshi; Takayuki Baba; Yasuhiro Watanabe; Atsushi Ike
We propose and demonstrate an FPGA-accelerated partial-image-matching engine for massive media-data searching systems. To take advantage of FPGA, a highly parallelized and pipelined architecture with an application-specific calculation was adopted. Our prototype system achieves 32 times better runtime performance than a CPU-based solution.
Archive | 2005
Masato Tatsuoka; Atsushi Ike
Archive | 2008
Masato Tatsuoka; Atsushi Ike
Archive | 2005
Teruhiko Kamigata; Shinichiro Tago; Atsushi Ike; Yoshimasa Takebe
Archive | 2006
Masato Tatsuoka; Atsushi Ike
Archive | 2010
Atsushi Ike; David Thach
Archive | 2010
Atsushi Ike
Archive | 2006
Masato Tatsuoka; Susumu Kashiwagi; Masahiko Toichi; Kazumasa Nakamura; Masayuki Tsuji; Takuya Hirata; Atsushi Ike