Yasumoto Tomita

Split capacitor DAC mismatch calibration in successive approximation ADC

A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS

A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSC-modulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to −5000ppm.

A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

A Dual-mode 2 ×21.5-22.3 Gb/s DQPSK or 1 × 39.8-44.6 Gb/s NRZ to 4 × 9.95-11.2 Gb/s SFI5.2-compliant two-chip SerDes for a family of 40 Gb/s optical transponders has been fabricated in 65 nm 12-metal CMOS. By demultiplexing to 16 × 2.5 Gb/s internally, all logic and testability functions could be implemented in standard-cell CMOS, resulting in total power consumption of 3 W, 75 % lower than commercial BiCMOS SFI5 40 Gb/s SerDes ICs. Chip area is 4 × 4 mm, and the ICs are flip-chip mounted into a quad flat-pack package.

A 10 Gb/s receiver with equalizer and on-chip ISI monitor in 0.11 /spl mu/m CMOS

This paper presents a 10 Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 /spl mu/m CMOS. The areas and power consumptions are 47 /spl mu/m/spl times/85 /spl mu/m and 13.2 mW for the equalizer and 145 /spl mu/m/spl times/80 /spl mu/m and 10 mW for the ISI monitor.

A dynamic offset control technique for comparator design in scaled CMOS technology

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-

This paper presents a 20-Gb/s simultaneous bidirectional transceiver using a resistor-transconductor (R-gm) hybrid in standard 0.11-mum CMOS. The R-gm hybrid separates the inbound signal from the signal line voltage and current without using a replica driver. It eliminates the need for precise matching between the replica- and main-driver characteristics, enabling a data rate of 20 Gb/s per differential pair, which is the highest reported for bidirectional signaling. The transceiver occupies 1.02 mm and consumes 260 mW at 20 Gb/s with a bit error rate of less than 10-12. The area and power overhead due to the hybrid are 0.002 mm2 and 7 mW, and correspond to 0.2% and 3% of the total transceiver area and power consumption.

\mu{\hbox {m}}

This paper presents a combined anti-aliasing filter and 2-tap feed-forward equalizer (AAF/FFE) as an analog front-end (AFE) for 2× blind ADC-based receivers. The front-end optimizes the channel/filter characteristics for data-rates of 2–10 Gb/s. The AAF bandwidth scales with the data-rate and the 2-tap FFE is designed without the need for noise-sensitive analog delay cells. The AAF/FFE is implemented in 65-nm CMOS, occupies 0.013 mm2, and consumes 2.4 mW at 10 Gb/s.

CMOS

ADC-based CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1–2], which requires a voltage-controlled oscillator or phase interpolator, both analog circuits, to adjust the phase of the sampling clock. To eliminate these analog circuits (and their phase control) in favor of an all-digital implementation, a blind-sampling ADC-based CDR (top of Fig. 8.6.1) samples the received signal at 2× without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set of samples in order to recover the phase and data [3–4]. The doubling of the sampling rate, however, increases the ADC power consumption or, equivalently, reduces the maximum baud rate due to the conversion-rate limitations of ADCs.

A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2–;10 Gb/s ADC-based receivers

A 20Gb/s simultaneous bidirectional transceiver uses a resistor-transconductor hybrid in a standard 0.11 mum CMOS process. The 7mW hybrid works in a continuous-time domain without any replica driver and eliminates the need for the precise matching between the replica- and main-driver characteristics