Atsushi Kazama

Development of low-cost and highly reliable wafer process package

A wafer level chip-scale-package (WLCSP) is expected to reduce the manufacturing cost of CSPs, but reliability of a solder joint for a large chip size of about 100 mm/sup 2/ without underfill assembly is still in question. To meet this needs, we have developed a highly reliable and low-cost WLCSP named wafer process package phase 2 (WPP-2). The package includes a built-in stress-relaxation layer for reducing the strain of the solder bumps. To lower the manufacturing cost of the package, the stress-relaxation layer is formed by printing. The Youngs modulus and the thickness of the stress relaxation layer were optimized by finite element analysis. The package was assumed to have 10/spl times/10 mm chip and 54 Sn-Ag-Cu solder balls of 400-/spl mu/m diameter placed as a grid array with the minimum pitch of 0.8 mm, and be mounted on a FR-4 motherboard. It was found that a thickness of 75-/spl mu/m and a Youngs modulus of 1000 MPa are necessary for assuring no failure up to 1000 cycles under temperature cycling between -55 and 125/spl deg/C. Accordingly, a resin with a Youngs modulus of about 1200 MPa at -55/spl deg/C was developed for the stress relaxation layer. High reliability of the simulated WPP-2 structure was confirmed by simplified test samples made of the developed resin. Fully processed WPP-2 samples were fabricated on an 8-inch wafer. The lifetime of the solder joints mounted on the FR-4 motherboard was evaluated by the temperature cycling test. The contact resistance of none of 50 samples increased by more than 20% even after 1400 cycles, and their lifetime to 50% failure was more than 3000 cycles.

Stress Relaxation Mechanism With a Ring-Shaped Beam for a Piezoresistive Three-Axis Accelerometer

A novel stress-relaxation structure with a ring-shaped beam for ensuring stability in a piezoresistive three-axis accelerometer assembled using wafer-level encapsulation and resin-mold packaging is proposed and evaluated in this paper. The reduction of the unstable increase in sensitivity due to buckling against three stress sources, i.e., the thermal stress in device fabrication, wafer bonding, and resin molding, was evaluated by both computer simulation and experiments on test samples. The measured increase in sensitivity due to stress during wafer bonding and resin molding was kept at 1.26 times using the ring-shaped beam, compared with 7.64 times when using a conventional straight beam. In addition, the standard deviation in the sensitivity of resin-molded samples was kept at 0.04 mV/G using the ring-shaped beam, compared with 2.19 mV/G using the straight beam. The sensitivity variation against the temperature change was also kept small and linear; thus, the effect of the ring-shaped beam was confirmed.

Low-insertion-loss compact 3D-MEMS optical matrix switch with 18 input/output ports

The paper describes a new three-dimensional (3D) MEMS optical switch. The switch consists of a collimator array for generating optical beams, and a MEMS mirror array for changing the directions of the beams. Each of the 18 optical ports can be either an input or an output, giving the switch a flexible configuration of 8/spl times/8, 2/spl times/16, and so on. The mirrors and the collimators are assembled passively in a compact package measuring 80/spl times/30/spl times/12 mm/sup 3/. The mean of measured insertion losses of all 64 paths in an 8/spl times/8 switch configuration was 1.1 dB; this confirms the low insertion loss of the developed switch.

Fabrication of a 35-channel optical scanner integrated by passive-self alignment using through-holes precisely formed by DRIE

A 35-channel optical scanner integrating a mirror array and a collimator-lens array was fabricated. The mirror array consists of a mirror substrate with 35 single-axis-rotational mirrors and an electrode substrate for actuating the corresponding mirror by electrostatic force. Each substrate includes two kinds of through-holes: one for passing a collimated-optical beam through, the other for inserting a precise pin for passive-self alignment of the mirror array and the collimator-lens array. To precisely form the through-holes suitable for passive-self alignment, deep reactive ion etching (DRIE) conditions were optimized. DRIE from both surfaces of a substrate under the optimized conditions - a C/sub 4/F/sub 8//SF/sub 6/ gas-flow ratio of 90% and a bias power in SF/sub 6/ gas of 110 W - can form through-holes with an average undercut of 3.4 /spl mu/m and an average sidewall angle of 89.9 degrees. By passive-self alignment, namely, inserting a pin into the fabricated through-hole and stacking the mirror array on the collimator-lens array, the measured assembly deviation of each substrate was less than 17.5 /spl mu/m.

Bonding strength characterization of eutectic-based WLP using molecular dynamics and wafer level shear testing

This paper investigated the bonding shear strength of eutectic-based wafer-level-packaging (WLP) for piezoresistive MEMS accelerometers. The bonding conditions were experimentally and analytically determined to realize higher shear strength without a diffusion of the solder material atoms to the adhesion layers: the energy dispersive X-ray (EDX) spectrometry and molecular dynamics (MD) simulations clarified the eutectic reaction of solder materials used in this research. Consequently, the bonding load of 9.8 kN and the temperature of 300 °C was found to be one of rational conditions because of a sufficient shear strength to endure the polishing process after the WLP and few diffusion of solder material atoms to the adhesion layer.

Fabrication of an optical beam scanning array integrating mirror and lens arrays by passive self-alignment using precisely formed through-holes

An optical beam scanning array (OBSA) integrating two mirror arrays and a collimator-lens array was fabricated. The passive self-alignment inserting a pin into a through-hole was carried out for integration of the mirror arrays and the collimator-lens array. The mirror arrays consist of a mirror substrate with 35 single-axis-rotational mirrors and an electrode substrate for actuating the corresponding mirror by electrostatic force. Each substrate includes two kinds of through-holes: one for passing a collimated-optical beam through, the other for inserting a pin. The conditions for deep-reactive-ion etching (DRIE) of silicon were optimized to form through-holes suitable for passive self-alignment. DRIE from both surfaces of a silicon wafer under the optimized DRIE conditions—a C4F8/SF6 gas-flow ratio of 90% and a bias power in SF6 gas of 110 W—formed precision through-holes with an average undercut of 3.4 µm and an average sidewall angle of 89.9°. The passive self-alignment then yielded an assembly deviation of less than 17.5 µm, which meets the specification of less than 50 µm. This means that passive self-alignment using a through-hole formed under the optimized DRIE conditions can be exploited to make OBSAs without requiring optical alignment of mirrors and lenses.