Cormac Michael O'connell

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS

From 90 nm and below, SoC integration is reaching the point where it makes technical and economic sense to integrate embedded DRAM (eDRAM) onto a die. While eDRAMs have 2.5x to 4x density compared to SRAMs and have lower soft-error rate they are slower in operation. In a conventional DRAM with a single column access device for read and write, a write operation is started only after the bitline sense amplifiers are turned on and the bitlines are well on their way to full restoration. This is to avoid destroying data due to premature access to global bitlines in the non-writing columns. This delay in the write operation increases row cycle time to allow the storage node to be fully written. Accelerating write cycle with early access only in the required columns requires a large area penalty because local sense amplifiers in one bank are usually grouped into a large block where all control signals are shared. Also an embedded DRAM in a standard 65 nm twin-tub SOI CMOS process that uses a local sense amplifier with VDD sensing and separate ports for read and write, with these operations synchronized with sensing is described. This eDRAM speeds up the row cycle with low area overhead by reducing the number of signals to control the ports and making write and read operations indistinguishable at the bank level.

A high-performance, high-density 28nm eDRAM technology with high-K/metal-gate

This paper presents industrys smallest 0.035um2 high performance embedded DRAM cell with cylinder-type Metal-Insulator-Metal (MIM) capacitor and integrated into 28nm High-K Metal Gate (HKMG) logic technology. This eDRAM memory features an HKMG CMOS compatible (low-thermal low-charging process) high-K MIM capacitor with extreme low leakage (<0.1fA/cell). Access transistor with HKMG shows excellent driving capability (>50uA/cell) with <1fA/cell leakage in 28nm cell and <3fA/cell in 20nm cell (0.021um2). We demonstrate first functional silicon success of 28nm eDRAM macro. 600/550 MHz operating frequency is achieved at typical/worse cases.

A high-performance low-power highly manufacturable embedded DRAM technology using backend hi-k MIM capacitor at 40nm node and beyond

A highly manufacturable embedded DRAM technology at 40nm node is presented. This report provides the characterization data of 128Mbit embedded DRAM test vehicle fabricated by 40nm eDRAM 200MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4Mb with configuration 32k×128 bits. The process is cost effective and compatible to our low power Logic core process with three additional critical masks to the base process. The DRAM memory cell consists of a high performance pass gate transistor and a metal-insulator-metal (MIM) storage capacitor with a cell size of 0.0583 um2 (< 1/4 of SRAM 0.242 um2) and small macro size of 0.145 mm2 per Mega bits (Mb). The stacked cell capacitor is formed using low temperature processed high-k dielectrics to achieve sufficient storage capacitance in DRAM cell. Low cell device leakage below 20 fA/cell at 105°C with silicided node process coupled with the high-k storage capacitance. The macro design for random access speed can operate from 25MHz to 200 MHz comparable to 6T SRAM. It has built-in ECC parity generation and correction circuits with memory storage space used for storing parity bits. The characterization is based on 200MHz, covering Vcc+/−15% at 125°C/ 105°C/ 25°C/ −40°C. Process corner skew includes core device corners TT/FS/SF/FF/SS and fast/slow cell device. Highly manufacturing yield of 128Mb macro is achieved to demonstrate the maturity of technology. The excellent cosmic ray (neutron) soft error rate (SER) performance of less than 4FITs/Mb is also achieved. The integration technologies can be applicable to the future embedded DRAM in 28nm, 20nm node and beyond.