Atul Maheshwari

Process Technology Variation

Moores law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moores law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

High fault tolerance for transient faults and low-power consumption are key objectives in the design of critical embedded systems. Systems like smart cards, PDAs, wearable computers, pacemakers, defibrillators, and other electronic gadgets must not only be designed for fault tolerance but also for ultra-low-power consumption due to limited battery life. In this paper, a highly accurate method of estimating fault tolerance in terms of mean time to failure (MTTF) is presented. The estimation is based on circuit-level simulations (HSPICE) and uses a double exponential current-source fault model. Using counters, it is shown that the transient fault tolerance and power dissipation of low-power circuits are at odds and allow for a power fault-tolerance tradeoff. Architecture and circuit level fault tolerance and low-power techniques are used to demonstrate and quantify this tradeoff. Estimates show that incorporation of these techniques results either in a design with an MTTF of 36 years and power consumption of 102 /spl mu/W or a design with an MTTF of 12 years and power consumption of 20 /spl mu/W. Depending on the criticality of the system and the power budget, certain techniques might be preferred over others, resulting in either a more fault tolerant or a lower power design, at the sacrifice of the alternative objective.

Differential current-sensing for on-chip interconnects

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.

Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS

Sensing current instead of voltage provides an alternative to signaling on the long wires that are increasingly limiting the performance of CMOS as it scales into the VDSM regime (<0.25 /spl mu/). Current-mode techniques have been proposed for sensing bit-lines. We present a comparative study of Current-sensing with the optimal repeater insertion technique for wires from 0.35 cm to 1.75 cm in length. Simulation results using SPICE for 0.18 /spl mu/ showed that current-sensing was faster and lower-power when compared to optimal repeater insertion technique. While the power dissipated by the optimal repeater circuit increased linearly with line length, power dissipated by the current-sensing circuit was almost constant for longer lines. Inductance had little effect on the differential current sensing technique.

An energy-aware active smart card

Despite recent advances in smart card technology, most modern smart cards continue to rely on card readers for power and clocking, creating a potential security gap. In this paper, we present an energy-aware smart card architecture that operates using an embedded battery and crystal. This low-power VLSI system is continually active and provides enhanced security through periodic internal update when the card is detached from a reader. Our architecture achieves reduced power consumption by deactivating the majority of its circuitry, including an embedded microcontroller, for the vast majority of the cards lifetime. A proof-of-concept prototype implementation of the architecture has been developed including register-transfer-level and gate-level designs which have been synthesized to silicon. To permit extended operation for up to 18 months, critical design logic has been implemented using ultralow-power (adiabatic) circuit techniques.

Trading off reliability and power-consumption in ultra-low power systems

Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consumption due to limited battery life. This paper explores architecture, logic and circuit level approaches to this tradeoff. Fault tolerance techniques at the architecture level can be broadly classified into spatial or temporal redundancy. Using an example of counters (binary and Gray) we show that temporal redundancy is best suited for these ultra-low power and low performance systems as it consumes 30% less power than an area redundant technique. Circuit techniques allow power-reliability tradeoffs of about 50% in each measure. A methodology is developed based on low-level fault simulation using SPICE, which allows detailed circuit models for both power consumption and reliability in current and future CMOS technology.

Sensing design issues in deep submicron CMOS SRAMs

In this paper, solutions to memory design issues in nanometer CMOS are presented. First, a comparative study between various sense-amplifiers is presented in 70nm CMOS technology. Impact of process variation is studied on the performance of these sense-amplifiers. An improved bit-line leakage compensation scheme is proposed to ensure proper sensing in presence of leakage. Performance benefit of up to 68% can be obtained using this technique.

Repeater and current-sensing hybrid circuits for on-chip interconnects

Designing interconnects is becoming an increasingly challenging problem with a few solutions. In this paper hybrid circuit based on the well known delay-optimal repeaters and the recently proposed differential current-sensing is presented. Comparison in terms of delay, power and area is drawn between various versions of the hybrid circuit with delay-optimal repeater insertion and differential current sensing in order to derive at the best possible solution. It is shown that driving 25% of the wire with repeaters and remaining with current-sensing is the best solution from delay standpoint (about 30% faster than delay-optimal repeaters). Not only do hybrid circuits consume less area, they are also a more acceptable solution from placement point of view due to fewer repeaters and a long segment of uninterrupted wire. Static power consumption inherited from differential current-sensing is the biggest drawback of the hybrid circuits.

Quantifying the impact of current-sensing on interconnect delay trends

This work tries to compare the performance of traditionally used repeaters with a recently proposed differential current-sensing signaling technique for present and future technologies. Several technology scaling models have been proposed for device and interconnect scaling. For this study, the Berkeley predictive technology model, the semiconductor industry association model and the Sylvester-Keutzer model are used. Percentage of chip reached in a clock cycle is used as a metric. This allows a better understanding of the impact of these circuit techniques on architecture and floorplanning issues. Results show that differential current-sensing signaling is significantly faster than repeaters for most of the scaling theories and hence allows for a larger coverage of chip in a clock cycle. If clock rates are scaled more aggressively (as they have been in the past), the gains for current-sensing can be even more significant. Any new circuit style presents design challenges and potential power and area tradeoffs. Despite these challenges, and as a motivation to overcome them, this paper shows a methodology and preliminary results that indicate opportunities for novel interconnect circuits.

Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects

In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits.