David E. Duarte

A clock power model to evaluate impact of architectural and technology optimizations

The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume at least a quarter of the power budget of existing microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock generation and distribution circuitry, including both the dynamic and leakage power components. The validation results show that the model is reasonably accurate, with the average deviation being within 10% of SPICE simulations. Access to this model can enable further research at high-level design stages in optimizing the system clock power. To illustrate this, a few architectural modifications are considered and their effect on the clock subsystem and the total system power budget is assessed.

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction

The mobile computing device market is projected to grow to 16.8 million units in 2004, representing an average annual growth rate of 28% over the five year forecast period. This brings the technologies that optimize system energy to the forefront. As circuits continue to scale in future, it would be important to optimize both leakage and dynamic energy. Effective optimization of leakage and dynamic energy consumption requires a vertical integration of techniques spanning from circuit to software levels. Schedule stacks in codes executing in VLIW architectures present an opportunity for such an integration. In this paper, we present compiler-directed techniques that take advantage of schedule slacks to optimize leakage and dynamic energy consumption. The proposed techniques have been incorporated into a cycle accurate simulator using parameters extracted from circuit level simulation. Our results show that a unified scheme that uses both dynamic and leakage energy reduction techniques is effective in reducing energy consumption.

Impact of scaling on the effectiveness of dynamic power reduction schemes

Power is considered to be the major limiter to the design of faster and more complex processors in the near future. In order to address this challenge, a combination of process, circuit design and micro-architectural changes are required Consequently, to focus optimization efforts in the right direction, the models proposed and studies performed in this work are a first step for understanding the relative importance of leakage and dynamic energy in future technologies. Further, we analyze the effectiveness of two energy reduction mechanisms that employ voltage scaling, namely, supply and threshold voltage selection. We consider the impact of imminent technology changes and packaging improvements while showing that neglecting the impact of temperature may lead to underestimating power savings by up to 19.5%.

Implications of technology scaling on leakage reduction techniques

The impact of technology scaling on three run-time leakage reduction techniques (input vector control, body bias control and power supply gating) is evaluated by determining limits and benefits, in terms of the potential leakage reduction, performance penalty, and area and power overhead in 0.25 um, 0.18 um, and 0.07 um technologies. HSPICE simulation results are estimations with various functional units and memory structures are presented to support a comprehensive analysis.

Analysis of soft error rate in flip-flops and scannable latches

Soft errors can be induced through radiation sources, with particles of low energy occurring far more frequently than particles of high energy. Therefore, smaller CMOS device are more easily affected by lower energy particles. Thus, soft errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating various designs in 70 nm, 1 V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the gate capacitance, the other improves the overall robustness of the circuit by replicating the master stage of the master-slave flip-flops, which leads to reduced power and area overhead.

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Thermal management (TM) allows the system architect to design a cooling solution based on real-life power consumption, not peak power. The on-die thermal sensor circuit, as the core of the TM system, monitors the on-die junction temperature (Tj). We present a novel high-linearity thermal sensor topology with built-in circuit support for correction of systematic shifts in the transfer function correction. Results obtained on the 65 nm Pentiumreg4 processor demonstrate the feasibility and effectiveness of the design.

Impact of technology scaling in the clock system power

The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed while a comprehensive framework for the estimation of systemwide (chip level) and clock sub-system power as function of technology scaling is presented. This framework is used to study and quantify the impact that various intensifying concerns associated with scaling (i.e., increased leakage currents, increased interwire capacitance) will have on clock energy and their relative impact on the overall system energy. The results obtained indicate that clock power will remain a significant contributor to the total chip power, as long as techniques are used to limit leakage power consumption.

Evaluating integrated hardware-software optimizations using a unified energy estimation framework

In embedded and portable applications, energy dissipation is a major design constraint. Designers must consider energy consumption. SimplePower evaluates the energy considering the system as a whole rather than just as a sum of parts, and concurrently supports both compiler and architectural experimentation. It includes a transition-sensitive, cycle-accurate datapath energy model that interfaces with analytical and transition-sensitive energy models for the memory, clock and bus subsystems, respectively. We analyzed the energy consumption of 10 codes from the multidimensional array domain, and find datapath energy hotspots, bottlenecks and helpful features. Optimized codes saved 21 percent more energy using the most recently used way-prediction cache scheme as compared to executing unoptimized codes from the multidimensional array domain.

Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process

Compact thermal sensors (<; 0.02 mm 2 ) are important for measuring thermal gradients in microprocessors and can directly affect the processors performance and power management. In this paper, the first 14 nm thermal sensor is reported. This sensor was fabricated in Intels 14 nm process, and is one of the first analog circuits reported in this technology. It has an area of 0.0087 mm 2 , can sense at a speed > 50 kS/sec, consumes 1.1 mW with a resolution of 0.5 °C, and has a resolution FOM of 5.7 nJ * C 2 . It is very close to the present BJT sensor state-of-the-art in its size, while being much faster and having a much better FOM than any of the compact BJT sensors.

Formulation and validation of an energy dissipation model for the clock generation circuitry and distribution networks

Proliferation of mobile devices and increasing design complexity have made low power consumption one of the major factors guiding digital design. The clock distribution and generation circuitry forms a critical component of current synchronous digital systems and is known to consume around a quarter of the power budget of current microprocessors. We propose and validate a high level model for evaluating the energy dissipation of the clock distribution and generation circuitry. Our validation results show that our model is fairly accurate and will be suitable for use in architectural level energy simulators. We believe access to this model can precipitate further research at high-level design stages in optimizing the system clock power.