Augustin Cathignol

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs

We present measurements for the standard deviation of the threshold voltage in n- and p-channel MOSFETs from the 45-nm low-power platform of STMicroelectronics. The measurements are compared with 3-D statistical simulations carried out with the Glasgow ldquoatomisticrdquo device simulator, considering random discrete dopants, line edge roughness, and the polysilicon granularity of the gate electrode. It was found that the surface potential pinning at the poly-Si grain boundaries (GBs), which is important for explaining the magnitude of the statistical variability of the n-channel MOSFETs, plays a negligible role in the p-channel case. First-principle simulation of low-angle silicon GBs is performed in order to explain the systematically observed differences in the threshold voltage standard deviation of the measured n- and p-channel MOSFETs.

Spacing impact on MOSFET mismatch

Many test structures embedded in various technologies were measured to study the spacing impact on MOSFET mismatch. This impact is showed to highly depend on technology, device family, device type and bias conditions. The study of spatial correlation allows to properly model spacing impact on mismatch: this analysis -in this paper focused on MOSFETs- may be extended to any device. Finally, a worst case model that only requires standard matched pairs at minimum spacing is proposed to provide designers the maximum matching degradation that may affect spaced devices.

Improved methodology for better accuracy on transistors matching characterization

An improved methodology for the characterization of matching parameters in MOSFETs and bipolar transistors is presented. Because of their statistical nature, only estimation of matching parameters can be provided from given measurements. Considering general /spl sigma//sub /spl Delta/p/ = A/sub p/ / /spl radic/(WL) transistor matching model, the aim of this paper is to discuss, for the first time, the most relevant matching parameter A/sub p/ estimation accuracy. Dispersion on A/sub p/ estimation when using conventional least squares regression on /spl sigma//sub /spl Delta/p/ vs. 1//spl radic/(WL) plots is analytically characterized. Then it is shown that replacing the conventional least squares regression by a weighted least squares regression leads to increased accuracy on A/sub p/ estimation and consequently allows a better detection of physical effects responsible for mismatch.

From MOSFET Matching Test Structures to Matching Data Utilization: Not an Ordinary Task

Delivering mismatch data that reflect design reality is a real challenge. Indeed, from test structures to final data utilization, many steps can be the source of distortion. The first possible source of distortion is linked to the differences in terms of environment and spacing that might exist between test structure transistors and circuit transistors. The second potential source of distortion is related to the measurements and extraction that can both add extra mismatch. Finally, the data treatment and utilization can constitute other error sources. In this paper, thanks to results from various test structures and device types, the main sources of distortion are pointed out in order to help to set up a reliable chain from matching test structures to matching data utilization.

High Threshold Voltage Matching Performance on Gate-All-Around MOSFET

For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on n-channel Gate-All-Around transistors (GAA) with both doped and undoped channel. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to suppress the dopant induced fluctuations contribution and provides an AVt parameter as low as 1.4 mV.?m, which is the best ever reported result on MOS transistors.

A Continuous Model for MOSFET VT Matching Considering Additional Length Effects

MOS transistor threshold voltage matching is usually modeled proportionally to reverse square root of gate area. Yet this model is not satisfactory when discontinuities are observed. In this paper, a continuous matching model with only two parameters is given. It is obtained by analyzing impact of short channel effects on matching degradation.

Abnormally High Current Local Fluctuations in Heavily Pocket-implanted Bulk Long MOSFET

For the first time, a strong current local fluctuations degradation on heavily pocket-implanted long devices is shown. This degradation, which is a serious concern for analog design, is attributed to the high potential barriers that stand at end sides of long devices and mainly control the device electrostatics. Because of the barriers height reduction as gate voltage increases, it is demonstrated that the excess fluctuations is highly gate bias dependent. But since current factor and threshold voltage do no longer enable a proper drain current modeling through whole gate bias, a new simple model based on the modulation of apparent threshold voltage with gate bias is introduced. This model allows a correct description of drain current and its excess fluctuations.