T. Skotnicki

Plasma wave detection of terahertz radiation by silicon field effects transistors: Responsivity and noise equivalent power

Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120–300nm have been studied as room temperature plasma wave detectors of 0.7THz electromagnetic radiation. In agreement with the plasma wave detection theory, the response was found to depend on the gate length and the gate bias. The obtained values of responsivity (⩽200V∕W) and noise equivalent power (⩾10−10W∕Hz0.5) demonstrate the potential of Si MOSFETs as sensitive detectors of terahertz radiation.

Plasma wave detection of sub-terahertz and terahertz radiation by silicon field-effect transistors

We report on experiments on photoresponse to sub-THz (120GHz) radiation of Si field-effect transistors (FETs) with nanometer and submicron gate lengths at 300K. The observed photoresponse is in agreement with predictions of the Dyakonov–Shur plasma wave detection theory. This is experimental evidence of the plasma wave detection by silicon FETs. The plasma wave parameters deduced from the experiments allow us to predict the nonresonant and resonant detection in THz range by nanometer size silicon devices—operating at room temperature.

Broadband terahertz imaging with highly sensitive silicon CMOS detectors

This paper investigates terahertz detectors fabricated in a low-cost 130 nm silicon CMOS technology. We show that the detectors consisting of a nMOS field effect transistor as rectifying element and an integrated bow-tie coupling antenna achieve a record responsivity above 5 kV/W and a noise equivalent power below 10 pW/Hz(0.5) in the important atmospheric window around 300 GHz and at room temperature. We demonstrate furthermore that the same detectors are efficient for imaging in a very wide frequency range from ~0.27 THz up to 1.05 THz. These results pave the way towards high sensitivity focal plane arrays in silicon for terahertz imaging.

Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia

The paradigm and the usage of CMOS are changing, and so are the requirements at all levels, from transistor to an entire CMOS system. The traditional drivers, such as speed and density of integration, are subject to other prerogatives related to variability, manufacturability, power consumption/dissipation (mobile products!), mix of varied digital and analog/RF functions (system-on-chip integration), etc. Controllability of variations and static leakage will add to, and in certain products prevail, over speed and density. Implications at all levels are multiple and are more diverse than just speed and smallness. The goal of the authors has been to see the problem globally from the product level and to place its components in their true proportions. Therefore, we will start with drawing the product-level picture and placing it in a historical perspective. Next, we will review the state of the art, the requirements, and solutions at the level of materials, transistor, and technology. Detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented in this paper.

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

Unexpected mobility degradation for very short devices : A new challenge for CMOS scaling

A new mobility degradation specific to short channel MOSFETs is studied and elucidated. Pocket implants/dopants pile-up, interface states/oxide charges, remote Coulomb scattering or ballisticity are insufficient to explain this degradation. The role of non-Coulombian (neutral) defects, which can be healed by increasing the annealing temperature, is evidenced

A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85/spl deg/C. Nondestructive reading is demonstrated at 25/spl deg/C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.

75 nm damascene metal gate and high-k integration for advanced CMOS devices

An advanced CMOS process has been proposed which include key features: 75 nm gate length damascene metal gate, high-k dielectrics with 1.35 nm EOT. Detailed characterisation (TEM, C-V, split C-V, charge pumping, LF noise, low and high temperature transport) demonstrate the high quality of the dielectric and interface. Low Ioff and low gate current make the technology attractive for low standby power applications.

SON (silicon on nothing)-a new device architecture for the ULSI era

A novel device architecture called SON (silicon on nothing) is proposed, allowing extremely thin buried oxides and silicon films to be fabricated and thereby provide better resistance to short channel effects (SCE) and DIBL than any other device architecture. SON devices are shown to present excellent I/sub on//I/sub off/ trade-off, V/sub th/ roll-off suppression down to 15 nm channel length, and to be free from the shortcomings of conventional SOI, such as self-heating, high S/D series resistances, and expensive SOI substrates since SON devices are fabricated on bulk silicon.

Dielectric pockets-a new concept of the junctions for deca-nanometric CMOS devices

A new concept of dielectric pockets is proposed allowing suppression of short-channel effects (SCEs) and DIBL without increasing the channel doping. The dielectric pockets have been implanted into 0.15-/spl mu/m PMOS devices showing substantial efficiency in reducing SCE and I/sub OFF/ current without altering the current drive. The dielectric pockets thus embody the ideal pocket architecture.