K. Rochereau

Quantitative Evaluation of Statistical Variability Sources in a 45-nm Technological Node LP N-MOSFET

A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the polysilicon bandgap that takes place along grain boundaries was evaluated, and polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the polysilicon-gate material and its deposition and annealing conditions.

65nm LP/GP mix low cost platform for multi-media wireless and consumer applications

A complete 65nm CMOS platform, called LP/GP mix, has been developed employing thick oxide transistor (1.0), low power (LP) and general purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO=1) speed equal to 7ps per stage (GP) and 6T-SRAM static power lower than 1 Op A/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with F/sub T/=160GHz for LP nMOS transistors.

MOSFET matching improvement in 65nm technology providing gain on both analog and SRAM performances

The 65 nm process has been optimized through thermal budget and implant of halo and LDD to reduce gate impact. It provides the best matching results ever reported to our knowledge, i.e. A/sub Vt/ of 2.1 and 1.9 mV./spl mu/m for NMOS and PMOS respectively. We demonstrate that such results provide relevant circuit performance improvement. For SRAM, a gain of more than 50% has been achieved on cell read current going from 4 down to 2.1 mV./spl mu/m. For analog applications, significant improvement is pointed out in terms of linearity and resolution.

Improved methodology for better accuracy on transistors matching characterization

An improved methodology for the characterization of matching parameters in MOSFETs and bipolar transistors is presented. Because of their statistical nature, only estimation of matching parameters can be provided from given measurements. Considering general /spl sigma//sub /spl Delta/p/ = A/sub p/ / /spl radic/(WL) transistor matching model, the aim of this paper is to discuss, for the first time, the most relevant matching parameter A/sub p/ estimation accuracy. Dispersion on A/sub p/ estimation when using conventional least squares regression on /spl sigma//sub /spl Delta/p/ vs. 1//spl radic/(WL) plots is analytically characterized. Then it is shown that replacing the conventional least squares regression by a weighted least squares regression leads to increased accuracy on A/sub p/ estimation and consequently allows a better detection of physical effects responsible for mismatch.

From MOSFET Matching Test Structures to Matching Data Utilization: Not an Ordinary Task

Delivering mismatch data that reflect design reality is a real challenge. Indeed, from test structures to final data utilization, many steps can be the source of distortion. The first possible source of distortion is linked to the differences in terms of environment and spacing that might exist between test structure transistors and circuit transistors. The second potential source of distortion is related to the measurements and extraction that can both add extra mismatch. Finally, the data treatment and utilization can constitute other error sources. In this paper, thanks to results from various test structures and device types, the main sources of distortion are pointed out in order to help to set up a reliable chain from matching test structures to matching data utilization.

High Threshold Voltage Matching Performance on Gate-All-Around MOSFET

For the first time, threshold voltage matching was measured on multiple gate transistors, and particularly on n-channel Gate-All-Around transistors (GAA) with both doped and undoped channel. Good matching performance is demonstrated on doped channel transistors, thanks to the absence of pocket nor halo implants. But most of all, it is shown that suppressing the channel doping allows to suppress the dopant induced fluctuations contribution and provides an AVt parameter as low as 1.4 mV.?m, which is the best ever reported result on MOS transistors.

A Continuous Model for MOSFET VT Matching Considering Additional Length Effects

MOS transistor threshold voltage matching is usually modeled proportionally to reverse square root of gate area. Yet this model is not satisfactory when discontinuities are observed. In this paper, a continuous matching model with only two parameters is given. It is obtained by analyzing impact of short channel effects on matching degradation.

Embedded FLASH memory thermal budget impact on core CMOS 90nm devices

In an embedded FLASH 90 nm technology, core devices behavior is modified by the thermal budget needed to process the specific FLASH dielectrics. When these steps are performed after the logic poly deposition, we observe two main kinds of changes: first the substrate doping is modified due to diffusion and segregation effects. Then, the poly morphology changes, this leads to larger poly grain size and gate doping change. To limit these effects and maintain the full compatibility with CMOS logic, thermal budget limitations are finally presented.