Avinash N. Ananthakrishnan

Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge

Modern microprocessors are evolving into system-on-a-chip designs with high integration levels, catering to ever-shrinking form factors. Portability without compromising performance is a driving market need. An architectural approach thats adaptive to and cognizant of workload behavior and platform physical constraints is indispensable to meeting these performance and efficiency goals. This article describes power-management innovations introduced on Intels Sandy Bridge microprocessor.

Power management on 14 nm Intel® Core− M processor

The desire to deliver breakthrough performance in a tablet form factor required several innovations in the 14nm Intel® flagship Core™ processor (Broadwell). Better frequency control algorithms including duty cycling graphics cores were developed to improve energy efficiency. New power sharing algorithms were developed to maximize performance of multiple compute domains within tight thermal and power delivery constraints. Innovations resulted in upto 50% increase in performance and upto 25% improvement in battery life over a Haswell system thermally constrained to a 4.5W fanless form factor.