Ayan Palchaudhuri

Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream

In this work, we have demonstrated the feasibility of hardware Trojan insertion in circuits mapped on FPGAs by direct modification of the FPGA configuration bitstream. The main challenge of this attack proved to be the lack of sufficient information in the public domain about the bitstream format and the internal architecture and configurability of the FPGA. Nevertheless, we were able to show that under certain constraints on the functionality, size and placement of the Trojan on the FPGA, it is possible to modify the configuration bitstream by a software program to insert a hardware Trojan in the design. The main strength of the attack lies in the fact that since the modification is at the configuration bitstream level, it bypasses all predeployment design validation mechanisms. We also propose some techniques to prevent the demonstrated attack. We hope that this work will raise awareness among FPGA users about the potency of the threat posed by this relatively simple attack and its improved variants. .

Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs

Scan flip -- flop insertion for aiding design for testability invites additional hardware overhead, thereby deteriorating the performance of the circuit. In this paper, we shall demonstrate a novel FPGA based implementation of inserting scan registers in commonly used Finite State Machines and pipelined data path circuits with no hardware overhead or compromise in performance. All our proposed designs have been realized using a relatively low -- level design methodology involving target FPGA family based primitive instantiation, coupled with their constrained placement on the Xilinx FPGA fabric. Implementation results clearly reveal the superiority of our proposed architectures in comparison to equivalent circuits derived through behavioral modeling with respect to area and speed. Additionally, our proposed scan register inserted circuits compare favourably with circuits designed without the scan flip -- flops. Coupled with this, lies the ease of an automated generation of the corresponding Hardware Description Language (HDL) and placement constraints and their portability among other advanced FPGA families from Xilinx.

Highly Compact Automated Implementation of Linear CA on FPGAs

The current literature on cellular automata (CA) mostly overlooks the fact that the perceived regularity and locality of interconnects in a CA are often logical rather than physical, and difficult to achieve in practical implementations. Optimized mapping, placement and routing of circuits are especially challenging for Field Programmable Gate Array (FPGA) platforms, which often result in low-performance implementations. We develop a design methodology for the automated implementation of low-resource, high-performance CA circuits, by optimal usage of the underlying FPGA architecture, direct primitive instantiation, and constrained placement. Case study for an 1-D CA circuit reveal higher performance, lower hardware resource requirement (by a factor of 0.5 X), acceptable power-delay product (PDP), and superior design scalability, in comparison to implementations derived by standard FPGA CAD tool design flow.

High Performance Integer Arithmetic Circuit Design on FPGA

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary User Constraints File. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students and professionals engaged in the domain of FPGA circuit optimization and implementation.

Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations

In order to meet superior performance metrics along with denser logic integration and device miniaturization, FPGAs have become more susceptible to transistor related aging, coupled with manufacturing defects owing to increased complexity in photolithographic techniques, thereby reducing the reliability and lifetime. In this paper, we propose certain built-in circuit techniques that are integrated with the original design, to localize the source of any hard or soft errors, if any, with tolerable penalty in performance, against acceptable time and/or hardware redundancy. Circuit realization on FPGA has been achieved through primitive instantiation and constrained placement, such that the exact location from which the fault has emanated can be traced, and bypassed for mapping any subsequent logic on the same FPGA. The adopted design paradigm which had earlier proved its potential for high performance FPGA based designs, has now been adopted to facilitate fault localization.

High performance bit-sliced pipelined comparator tree for FPGAs

In this paper, we have implemented high performance FPGA based pipelined tree architectures for a combined unsigned and twos complement comparator, and an equality comparator which checks whether the sum of two numbers is equal to a third number. The comparator architectures deviate from the combined Look-Up Table (LUT) and carry chain based implementation which is inferred by the Xilinx Synthesis Tool. The feasibility of this work comes from the increased device density offered by the 6 and 7 series FPGA architectures from Xilinx, where every dual output function derived from a single LUT can be registered using a flip-flop present within the same slice as that of the LUT. Pipelining a tree based architecture completely eliminates the requirement of any synchronization registers for balancing the arrival time of the inputs and outputs, and their associated placement and routing challenges. The architecture has been realized through primitive instantiation of the logic elements to ensure packing of the dual output functions into a single LUT wherever possible, and the placement of the LUTs on the FPGA fabric using appropriate placement constraints. Implementation results clearly reveal the superiority of our design paradigm over behavioral style of modeling, where our proposed architectures consume less area, and operates at a higher speed in comparison to an identical circuit realized using behavioral descriptions.

Automated Design of High Performance Integer Arithmetic Cores on FPGA

We present the principles of operation and functioning of a CAD software tool for the automated realization of high performance integer arithmetic circuits targeting Xilinx Field Programmable Gate Arrays (FPGAs). The key ideas behind the improvement of circuit performance are optimal usage of the hardware primitives available on the Xilinx FPGA platform, as well as regular, careful and constrained placement of the circuit building blocks on the FPGA fabric. The bit - sliced architectures of our proposed designs allow us to automatically generate synthesizable, platform - specific structural Hardware Description Language (HDL) code for the proposed circuits, as well as the placement constraint files needed to control the placement of the design on the given FPGA fabric. Compared against circuits implemented using existing approaches and those automatically generated using existing CAD tools, our automatically generated implementations demonstrate significant speed improvement.

Fast Carry Chain Based Architectures for Two’s Complement to CSD Recoding on FPGAs

Canonic signed digit (CSD) representation is a popular choice for realization of high speed, area efficient VLSI architectures in digital signal processing (DSP). In this paper, we address efficient FPGA based architectures for high speed two’s complement to CSD recoding using serial and look-ahead based circuitry. We have also demonstrated the feasibility of a scan based design approach integrated into the original design to facilitate fault localization. The generation of the circuit descriptions have been automated making it an attractive option for commercial viability of such a design approach.

Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs

The ever increasing demand to push the envelope for achieving superlative metrics of VLSI circuit performance along with denser logic packing and miniaturization of device dimensions, has rendered FPGAs to be more vulnerable to reliability hazards. This has led to reducing of the reliability and lifetime of VLSI chips. In this paper, we have proposed certain circuit techniques which comes along with the original design, to detect the presence of faulty FPGA logic slices, without significant compromise in performance. Primitive instantiation and constrained placement based approach was adopted for the circuit realizations to facilitate tracing of the exact faulty location, so that the faulty zones may be conveniently bypassed for fault-free circuit operation.

Architecture of Target FPGA Platform

This chapter provides an insight into the architecture of Configurable Logic Blocks (CLBs), the basic building blocks of a FPGA, including details of the Look-Up Tables, wide function multiplexers, carry chains, flip-flops, and DSP slices . It also gives an overview of the different modes of implementation supported by Xilinx ISE to realize arithmetic functions.